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[GlobalISel] Fix AArch64 ICMP instruction selection 

Differential Revision: https://reviews.llvm.org/D28175

llvm-svn: 291097
This commit is contained in:
Kristof Beyls 2017-01-05 10:16:08 +00:00
parent 9f4a935b2a
commit 2252440b81
2 changed files with 10 additions and 6 deletions
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10
llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
View File

@ -1071,8 +1071,12 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
return false;
}
const AArch64CC::CondCode CC = changeICMPPredToAArch64CC(
(CmpInst::Predicate)I.getOperand(1).getPredicate());
// CSINC increments the result by one when the condition code is false.
// Therefore, we have to invert the predicate to get an increment by 1 when
// the predicate is true.
const AArch64CC::CondCode invCC =
changeICMPPredToAArch64CC(CmpInst::getInversePredicate(
(CmpInst::Predicate)I.getOperand(1).getPredicate()));
MachineInstr &CmpMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
.addDef(ZReg)
@ -1084,7 +1088,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
.addDef(I.getOperand(0).getReg())
.addUse(AArch64::WZR)
.addUse(AArch64::WZR)
.addImm(CC);
.addImm(invCC);
constrainSelectedInstRegOperands(CmpMI, TII, TRI, RBI);
constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI);

6
llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
View File

@ -2836,13 +2836,13 @@ registers:
# CHECK: body:
# CHECK: %wzr = SUBSWrr %0, %0, implicit-def %nzcv
# CHECK: %1 = CSINCWr %wzr, %wzr, 0, implicit %nzcv
# CHECK: %1 = CSINCWr %wzr, %wzr, 1, implicit %nzcv
# CHECK: %xzr = SUBSXrr %2, %2, implicit-def %nzcv
# CHECK: %3 = CSINCWr %wzr, %wzr, 2, implicit %nzcv
# CHECK: %3 = CSINCWr %wzr, %wzr, 3, implicit %nzcv
# CHECK: %xzr = SUBSXrr %4, %4, implicit-def %nzcv
# CHECK: %5 = CSINCWr %wzr, %wzr, 1, implicit %nzcv
# CHECK: %5 = CSINCWr %wzr, %wzr, 0, implicit %nzcv
body: |
bb.0: