From 22274934f43681dc37d5bf39f99308ce443308d9 Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Fri, 11 Nov 2016 08:27:37 +0000 Subject: [PATCH] [ARM] Add plumbing for GlobalISel Add GlobalISel skeleton, up to the point where we can select a ret void. llvm-svn: 286573 --- llvm/lib/Target/ARM/ARMCallLowering.cpp | 47 +++++++++++ llvm/lib/Target/ARM/ARMCallLowering.h | 37 ++++++++ .../lib/Target/ARM/ARMInstructionSelector.cpp | 36 ++++++++ llvm/lib/Target/ARM/ARMInstructionSelector.h | 42 ++++++++++ llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 28 +++++++ llvm/lib/Target/ARM/ARMLegalizerInfo.h | 29 +++++++ llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 27 ++++++ llvm/lib/Target/ARM/ARMRegisterBankInfo.h | 29 +++++++ llvm/lib/Target/ARM/ARMSubtarget.cpp | 22 ++++- llvm/lib/Target/ARM/ARMSubtarget.h | 14 ++++ llvm/lib/Target/ARM/ARMTargetMachine.cpp | 84 ++++++++++++++++++- llvm/lib/Target/ARM/CMakeLists.txt | 16 ++++ llvm/lib/Target/ARM/LLVMBuild.txt | 2 +- .../ARM/GlobalISel/arm-irtranslator.ll | 9 ++ .../test/CodeGen/ARM/GlobalISel/lit.local.cfg | 2 + 15 files changed, 419 insertions(+), 5 deletions(-) create mode 100644 llvm/lib/Target/ARM/ARMCallLowering.cpp create mode 100644 llvm/lib/Target/ARM/ARMCallLowering.h create mode 100644 llvm/lib/Target/ARM/ARMInstructionSelector.cpp create mode 100644 llvm/lib/Target/ARM/ARMInstructionSelector.h create mode 100644 llvm/lib/Target/ARM/ARMLegalizerInfo.cpp create mode 100644 llvm/lib/Target/ARM/ARMLegalizerInfo.h create mode 100644 llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp create mode 100644 llvm/lib/Target/ARM/ARMRegisterBankInfo.h create mode 100644 llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll create mode 100644 llvm/test/CodeGen/ARM/GlobalISel/lit.local.cfg diff --git a/llvm/lib/Target/ARM/ARMCallLowering.cpp b/llvm/lib/Target/ARM/ARMCallLowering.cpp new file mode 100644 index 000000000000..a7ef6e79591d --- /dev/null +++ b/llvm/lib/Target/ARM/ARMCallLowering.cpp @@ -0,0 +1,47 @@ +//===-- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering -----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the lowering of LLVM calls to machine code calls for +/// GlobalISel. +/// +//===----------------------------------------------------------------------===// + +#include "ARMCallLowering.h" + +#include "ARMBaseInstrInfo.h" +#include "ARMISelLowering.h" + +#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" + +using namespace llvm; + +#ifndef LLVM_BUILD_GLOBAL_ISEL +#error "This shouldn't be built without GISel" +#endif + +ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI) + : CallLowering(&TLI) {} + +bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, + const Value *Val, unsigned VReg) const { + // We're currently only handling void returns + if (Val != nullptr) + return false; + + AddDefaultPred(MIRBuilder.buildInstr(ARM::BX_RET)); + + return true; +} + +bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, + const Function &F, + ArrayRef VRegs) const { + return F.arg_empty(); +} diff --git a/llvm/lib/Target/ARM/ARMCallLowering.h b/llvm/lib/Target/ARM/ARMCallLowering.h new file mode 100644 index 000000000000..10620462be9d --- /dev/null +++ b/llvm/lib/Target/ARM/ARMCallLowering.h @@ -0,0 +1,37 @@ +//===-- llvm/lib/Target/ARM/ARMCallLowering.h - Call lowering -------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file describes how to lower LLVM calls to machine code calls. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_ARM_ARMCALLLOWERING +#define LLVM_LIB_TARGET_ARM_ARMCALLLOWERING + +#include "llvm/CodeGen/CallingConvLower.h" +#include "llvm/CodeGen/GlobalISel/CallLowering.h" +#include "llvm/CodeGen/ValueTypes.h" + +namespace llvm { + +class ARMTargetLowering; + +class ARMCallLowering : public CallLowering { +public: + ARMCallLowering(const ARMTargetLowering &TLI); + + bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val, + unsigned VReg) const override; + + bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, + ArrayRef VRegs) const override; +}; +} // End of namespace llvm +#endif diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp new file mode 100644 index 000000000000..5905963bcb35 --- /dev/null +++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp @@ -0,0 +1,36 @@ +//===- ARMInstructionSelector.cpp ----------------------------*- C++ -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// \file +/// This file implements the targeting of the InstructionSelector class for ARM. +/// \todo This should be generated by TableGen. +//===----------------------------------------------------------------------===// + +#include "ARMInstructionSelector.h" +#include "ARMRegisterBankInfo.h" +#include "ARMSubtarget.h" +#include "ARMTargetMachine.h" +#include "llvm/Support/Debug.h" + +#define DEBUG_TYPE "arm-isel" + +using namespace llvm; + +#ifndef LLVM_BUILD_GLOBAL_ISEL +#error "You shouldn't build this" +#endif + +ARMInstructionSelector::ARMInstructionSelector(const ARMBaseTargetMachine &TM, + const ARMSubtarget &STI, + const ARMRegisterBankInfo &RBI) + : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()), + TRI(*STI.getRegisterInfo()), RBI(RBI) {} + +bool ARMInstructionSelector::select(llvm::MachineInstr &I) const { + return !isPreISelGenericOpcode(I.getOpcode()); +} diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.h b/llvm/lib/Target/ARM/ARMInstructionSelector.h new file mode 100644 index 000000000000..3b32ce4746d2 --- /dev/null +++ b/llvm/lib/Target/ARM/ARMInstructionSelector.h @@ -0,0 +1,42 @@ +//===- ARMInstructionSelector ------------------------------------*- C++ -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// \file +/// This file declares the targeting of the InstructionSelector class for ARM. +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_ARM_ARMINSTRUCTIONSELECTOR_H +#define LLVM_LIB_TARGET_ARM_ARMINSTRUCTIONSELECTOR_H + +#include "llvm/CodeGen/GlobalISel/InstructionSelector.h" + +namespace llvm { +class ARMBaseInstrInfo; +class ARMBaseRegisterInfo; +class ARMBaseTargetMachine; +class ARMRegisterBankInfo; +class ARMSubtarget; + +class ARMInstructionSelector : public InstructionSelector { +public: + ARMInstructionSelector(const ARMBaseTargetMachine &TM, + const ARMSubtarget &STI, + const ARMRegisterBankInfo &RBI); + + virtual bool select(MachineInstr &I) const override; + +private: + const ARMBaseTargetMachine &TM; + const ARMSubtarget &STI; + const ARMBaseInstrInfo &TII; + const ARMBaseRegisterInfo &TRI; + const ARMRegisterBankInfo &RBI; +}; + +} // End llvm namespace. +#endif diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp new file mode 100644 index 000000000000..f0f00f0acbc7 --- /dev/null +++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp @@ -0,0 +1,28 @@ +//===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// \file +/// This file implements the targeting of the Machinelegalizer class for ARM. +/// \todo This should be generated by TableGen. +//===----------------------------------------------------------------------===// + +#include "ARMLegalizerInfo.h" +#include "llvm/CodeGen/ValueTypes.h" +#include "llvm/IR/DerivedTypes.h" +#include "llvm/IR/Type.h" +#include "llvm/Target/TargetOpcodes.h" + +using namespace llvm; + +#ifndef LLVM_BUILD_GLOBAL_ISEL +#error "You shouldn't build this" +#endif + +ARMLegalizerInfo::ARMLegalizerInfo() { + computeTables(); +} diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.h b/llvm/lib/Target/ARM/ARMLegalizerInfo.h new file mode 100644 index 000000000000..ca3eea81271b --- /dev/null +++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.h @@ -0,0 +1,29 @@ +//===- ARMLegalizerInfo ------------------------------------------*- C++ -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// \file +/// This file declares the targeting of the Machinelegalizer class for ARM. +/// \todo This should be generated by TableGen. +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_ARM_ARMMACHINELEGALIZER_H +#define LLVM_LIB_TARGET_ARM_ARMMACHINELEGALIZER_H + +#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" + +namespace llvm { + +class LLVMContext; + +/// This class provides the information for the target register banks. +class ARMLegalizerInfo : public LegalizerInfo { +public: + ARMLegalizerInfo(); +}; +} // End llvm namespace. +#endif diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp new file mode 100644 index 000000000000..561916d4d94c --- /dev/null +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -0,0 +1,27 @@ +//===- ARMRegisterBankInfo.cpp -----------------------------------*- C++ -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// \file +/// This file implements the targeting of the RegisterBankInfo class for ARM. +/// \todo This should be generated by TableGen. +//===----------------------------------------------------------------------===// + +#include "ARMRegisterBankInfo.h" +#include "llvm/CodeGen/GlobalISel/RegisterBank.h" +#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" + +using namespace llvm; + +#ifndef LLVM_BUILD_GLOBAL_ISEL +#error "You shouldn't build this" +#endif + +ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI) + : RegisterBankInfo(nullptr, 0) {} diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.h b/llvm/lib/Target/ARM/ARMRegisterBankInfo.h new file mode 100644 index 000000000000..f58f6df737d3 --- /dev/null +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.h @@ -0,0 +1,29 @@ +//===- ARMRegisterBankInfo ---------------------------------------*- C++ -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// \file +/// This file declares the targeting of the RegisterBankInfo class for ARM. +/// \todo This should be generated by TableGen. +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H +#define LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H + +#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" + +namespace llvm { + +class TargetRegisterInfo; + +/// This class provides the information for the target register banks. +class ARMRegisterBankInfo final : public RegisterBankInfo { +public: + ARMRegisterBankInfo(const TargetRegisterInfo &TRI); +}; +} // End llvm namespace. +#endif diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 550fef03b67a..1cd1ac7afb31 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -98,7 +98,27 @@ ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU, : !isThumb() ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this) : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)), - TLInfo(TM, *this) {} + TLInfo(TM, *this), GISel() {} + +const CallLowering *ARMSubtarget::getCallLowering() const { + assert(GISel && "Access to GlobalISel APIs not set"); + return GISel->getCallLowering(); +} + +const InstructionSelector *ARMSubtarget::getInstructionSelector() const { + assert(GISel && "Access to GlobalISel APIs not set"); + return GISel->getInstructionSelector(); +} + +const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const { + assert(GISel && "Access to GlobalISel APIs not set"); + return GISel->getLegalizerInfo(); +} + +const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const { + assert(GISel && "Access to GlobalISel APIs not set"); + return GISel->getRegBankInfo(); +} bool ARMSubtarget::isXRaySupported() const { // We don't currently suppport Thumb, but Windows requires Thumb. diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index cf53831defe1..c3a355b85a96 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -25,6 +25,7 @@ #include "Thumb1InstrInfo.h" #include "Thumb2InstrInfo.h" #include "llvm/ADT/Triple.h" +#include "llvm/CodeGen/GlobalISel/GISelAccessor.h" #include "llvm/IR/DataLayout.h" #include "llvm/MC/MCInstrItineraries.h" #include "llvm/Target/TargetSubtargetInfo.h" @@ -350,6 +351,9 @@ public: ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle); + /// This object will take onwership of \p GISelAccessor. + void setGISelAccessor(GISelAccessor &GISel) { this->GISel.reset(&GISel); } + /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size /// that still makes it profitable to inline the call. unsigned getMaxInlineSizeThreshold() const { @@ -379,6 +383,11 @@ public: return &InstrInfo->getRegisterInfo(); } + const CallLowering *getCallLowering() const override; + const InstructionSelector *getInstructionSelector() const override; + const LegalizerInfo *getLegalizerInfo() const override; + const RegisterBankInfo *getRegBankInfo() const override; + private: ARMSelectionDAGInfo TSInfo; // Either Thumb1FrameLowering or ARMFrameLowering. @@ -387,6 +396,11 @@ private: std::unique_ptr InstrInfo; ARMTargetLowering TLInfo; + /// Gather the accessor points to GlobalISel-related APIs. + /// This is used to avoid ifndefs spreading around while GISel is + /// an optional library. + std::unique_ptr GISel; + void initializeEnvironment(); void initSubtargetFeatures(StringRef CPU, StringRef FS); ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS); diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index 4ef882a7bc82..355a499b7d53 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -10,11 +10,19 @@ // //===----------------------------------------------------------------------===// -#include "ARM.h" -#include "ARMFrameLowering.h" #include "ARMTargetMachine.h" +#include "ARM.h" +#include "ARMCallLowering.h" +#include "ARMFrameLowering.h" +#include "ARMInstructionSelector.h" +#include "ARMLegalizerInfo.h" +#include "ARMRegisterBankInfo.h" #include "ARMTargetObjectFile.h" #include "ARMTargetTransformInfo.h" +#include "llvm/CodeGen/GlobalISel/IRTranslator.h" +#include "llvm/CodeGen/GlobalISel/InstructionSelect.h" +#include "llvm/CodeGen/GlobalISel/Legalizer.h" +#include "llvm/CodeGen/GlobalISel/RegBankSelect.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/IR/Function.h" @@ -22,8 +30,8 @@ #include "llvm/MC/MCAsmInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/FormattedStream.h" -#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetParser.h" +#include "llvm/Support/TargetRegistry.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Transforms/Scalar.h" using namespace llvm; @@ -57,6 +65,7 @@ extern "C" void LLVMInitializeARMTarget() { RegisterTargetMachine B(getTheThumbBETarget()); PassRegistry &Registry = *PassRegistry::getPassRegistry(); + initializeGlobalISel(Registry); initializeARMLoadStoreOptPass(Registry); initializeARMPreAllocLoadStoreOptPass(Registry); } @@ -231,6 +240,29 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT, ARMBaseTargetMachine::~ARMBaseTargetMachine() {} +#ifdef LLVM_BUILD_GLOBAL_ISEL +namespace { +struct ARMGISelActualAccessor : public GISelAccessor { + std::unique_ptr CallLoweringInfo; + std::unique_ptr InstSelector; + std::unique_ptr Legalizer; + std::unique_ptr RegBankInfo; + const CallLowering *getCallLowering() const override { + return CallLoweringInfo.get(); + } + const InstructionSelector *getInstructionSelector() const override { + return InstSelector.get(); + } + const class LegalizerInfo *getLegalizerInfo() const override { + return Legalizer.get(); + } + const RegisterBankInfo *getRegBankInfo() const override { + return RegBankInfo.get(); + } +}; +} // End anonymous namespace. +#endif + const ARMSubtarget * ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const { Attribute CPUAttr = F.getFnAttribute("target-cpu"); @@ -263,6 +295,24 @@ ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const { resetTargetOptions(F); I = llvm::make_unique(TargetTriple, CPU, FS, *this, isLittle); } + +#ifndef LLVM_BUILD_GLOBAL_ISEL + GISelAccessor *GISel = new GISelAccessor(); +#else + ARMGISelActualAccessor *GISel = new ARMGISelActualAccessor(); + GISel->CallLoweringInfo.reset(new ARMCallLowering(*I->getTargetLowering())); + GISel->Legalizer.reset(new ARMLegalizerInfo()); + + auto *RBI = new ARMRegisterBankInfo(*I->getRegisterInfo()); + + // FIXME: At this point, we can't rely on Subtarget having RBI. + // It's awkward to mix passing RBI and the Subtarget; should we pass + // TII/TRI as well? + GISel->InstSelector.reset(new ARMInstructionSelector(*this, *I, *RBI)); + + GISel->RegBankInfo.reset(RBI); +#endif + I->setGISelAccessor(*GISel); return I.get(); } @@ -353,6 +403,12 @@ public: void addIRPasses() override; bool addPreISel() override; bool addInstSelector() override; +#ifdef LLVM_BUILD_GLOBAL_ISEL + bool addIRTranslator() override; + bool addLegalizeMachineIR() override; + bool addRegBankSelect() override; + bool addGlobalInstructionSelect() override; +#endif void addPreRegAlloc() override; void addPreSched2() override; void addPreEmitPass() override; @@ -413,6 +469,28 @@ bool ARMPassConfig::addInstSelector() { return false; } +#ifdef LLVM_BUILD_GLOBAL_ISEL +bool ARMPassConfig::addIRTranslator() { + addPass(new IRTranslator()); + return false; +} + +bool ARMPassConfig::addLegalizeMachineIR() { + addPass(new Legalizer()); + return false; +} + +bool ARMPassConfig::addRegBankSelect() { + addPass(new RegBankSelect()); + return false; +} + +bool ARMPassConfig::addGlobalInstructionSelect() { + addPass(new InstructionSelect()); + return false; +} +#endif + void ARMPassConfig::addPreRegAlloc() { if (getOptLevel() != CodeGenOpt::None) { addPass(createMLxExpansionPass()); diff --git a/llvm/lib/Target/ARM/CMakeLists.txt b/llvm/lib/Target/ARM/CMakeLists.txt index d96acb6c6670..0c57a3e3166b 100644 --- a/llvm/lib/Target/ARM/CMakeLists.txt +++ b/llvm/lib/Target/ARM/CMakeLists.txt @@ -13,6 +13,21 @@ tablegen(LLVM ARMGenSubtargetInfo.inc -gen-subtarget) tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler) add_public_tablegen_target(ARMCommonTableGen) +# Add GlobalISel files if the user wants to build it. +set(GLOBAL_ISEL_FILES + ARMCallLowering.cpp + ARMInstructionSelector.cpp + ARMLegalizerInfo.cpp + ARMRegisterBankInfo.cpp + ) + +if(LLVM_BUILD_GLOBAL_ISEL) + set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES}) +else() + set(GLOBAL_ISEL_BUILD_FILES "") + set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES}) +endif() + add_llvm_target(ARMCodeGen A15SDOptimizer.cpp ARMAsmPrinter.cpp @@ -45,6 +60,7 @@ add_llvm_target(ARMCodeGen Thumb2InstrInfo.cpp Thumb2SizeReduction.cpp ARMComputeBlockSize.cpp + ${GLOBAL_ISEL_BUILD_FILES} ) add_subdirectory(TargetInfo) diff --git a/llvm/lib/Target/ARM/LLVMBuild.txt b/llvm/lib/Target/ARM/LLVMBuild.txt index 9ed51dfda0f1..80d39610574f 100644 --- a/llvm/lib/Target/ARM/LLVMBuild.txt +++ b/llvm/lib/Target/ARM/LLVMBuild.txt @@ -31,5 +31,5 @@ has_jit = 1 type = Library name = ARMCodeGen parent = ARM -required_libraries = ARMAsmPrinter ARMDesc ARMInfo Analysis AsmPrinter CodeGen Core MC Scalar SelectionDAG Support Target +required_libraries = ARMAsmPrinter ARMDesc ARMInfo Analysis AsmPrinter CodeGen Core MC Scalar SelectionDAG Support Target GlobalISel add_to_library_groups = ARM diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll new file mode 100644 index 000000000000..68dd820eda6b --- /dev/null +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll @@ -0,0 +1,9 @@ +; RUN: llc -mtriple arm-unknown -global-isel -stop-after=irtranslator %s -o - | FileCheck %s + +define void @test_void_return() { +; CHECK-LABEL: name: test_void_return +; CHECK: BX_RET 14, _ +entry: + ret void +} + diff --git a/llvm/test/CodeGen/ARM/GlobalISel/lit.local.cfg b/llvm/test/CodeGen/ARM/GlobalISel/lit.local.cfg new file mode 100644 index 000000000000..e99d1bb8446c --- /dev/null +++ b/llvm/test/CodeGen/ARM/GlobalISel/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'global-isel' in config.root.available_features: + config.unsupported = True