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reduce indentation and improve comments, no functionality change. 

llvm-svn: 122389
This commit is contained in:
Chris Lattner 2010-12-22 07:36:50 +00:00
parent 7089250f5a
commit 222374d886
1 changed files with 53 additions and 51 deletions
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22
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -4242,7 +4242,6 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
// of the extended byte. This is not worth optimizing for.
if (ShAmt >= VT.getSizeInBits())
return SDValue();
}
}
@ -4250,20 +4249,26 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
// we can fold the truncate through the shift.
unsigned ShLeftAmt = 0;
if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
ExtVT == VT &&
TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
ShLeftAmt = N01->getZExtValue();
N0 = N0.getOperand(0);
}
}
// If we haven't found a load, we can't narrow it. Don't transform one with
// multiple uses, this would require adding a new load.
if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
// Don't change the width of a volatile load.
cast<LoadSDNode>(N0)->isVolatile())
return SDValue();
// Do not generate loads of non-round integer types since these can
// be expensive (and would be wrong if the type is not byte sized).
if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() &&
cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() >= EVTBits &&
// Do not change the width of a volatile load.
!cast<LoadSDNode>(N0)->isVolatile()) {
if (!ExtVT.isRound() ||
cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
return SDValue();
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
EVT PtrType = N0.getOperand(1).getValueType();
@ -4310,9 +4315,6 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
return Result;
}
return SDValue();
}
SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);