DetectDeadLanes: Increase precision when detecting undef inputs
In case of COPY-like instruction we may be able to deduce that a certain input is unused, based on the used lanes of the register defined by the instruction. This even works accross otherwise incompatible copies (no need to have compatible lanemasks, completely unused operands are still completely unused). It even makes sense to redo the analysis in this case since we gained information for a case we previously stopped at because of the incompatible masks. llvm-svn: 268815
This commit is contained in:
Matthias Braun
parent
8f429ead58
commit
22152acf7b
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@ -30,6 +30,7 @@
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#include <vector>
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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@ -73,7 +74,7 @@ private:
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/// Given a bitmask \p UsedLanes for the used lanes on a def output of a
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/// COPY-like instruction determine the lanes used on the use operands
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/// and call addUsedLanesOnOperand() for them.
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void transferUsedLanesStep(const MachineOperand &Def, LaneBitmask UsedLanes);
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void transferUsedLanesStep(const MachineInstr &MI, LaneBitmask UsedLanes);
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/// Given a use regiser operand \p Use and a mask of defined lanes, check
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/// if the operand belongs to a lowersToCopies() instruction, transfer the
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@ -87,9 +88,21 @@ private:
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LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
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LaneBitmask DefinedLanes) const;
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/// Given a mask \p UsedLanes used from the output of instruction \p MI
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/// determine which lanes are used from operand \p MO of this instruction.
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LaneBitmask transferUsedLanes(const MachineInstr &MI, LaneBitmask UsedLanes,
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const MachineOperand &MO) const;
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bool runOnce(MachineFunction &MF);
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LaneBitmask determineInitialDefinedLanes(unsigned Reg);
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LaneBitmask determineInitialUsedLanes(unsigned Reg);
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bool isUndefRegAtInput(const MachineOperand &MO,
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const VRegInfo &RegInfo) const;
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bool isUndefInput(const MachineOperand &MO, bool *CrossCopy) const;
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const MachineRegisterInfo *MRI;
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const TargetRegisterInfo *TRI;
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@ -201,39 +214,40 @@ void DetectDeadLanes::addUsedLanesOnOperand(const MachineOperand &MO,
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PutInWorklist(MORegIdx);
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}
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void DetectDeadLanes::transferUsedLanesStep(const MachineOperand &Def,
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void DetectDeadLanes::transferUsedLanesStep(const MachineInstr &MI,
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LaneBitmask UsedLanes) {
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const MachineInstr &MI = *Def.getParent();
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for (const MachineOperand &MO : MI.uses()) {
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if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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continue;
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LaneBitmask UsedOnMO = transferUsedLanes(MI, UsedLanes, MO);
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addUsedLanesOnOperand(MO, UsedOnMO);
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}
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}
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LaneBitmask DetectDeadLanes::transferUsedLanes(const MachineInstr &MI,
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LaneBitmask UsedLanes,
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const MachineOperand &MO) const {
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unsigned OpNum = MI.getOperandNo(&MO);
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assert(lowersToCopies(MI) && DefinedByCopy[
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TargetRegisterInfo::virtReg2Index(MI.getOperand(0).getReg())]);
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switch (MI.getOpcode()) {
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case TargetOpcode::COPY:
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case TargetOpcode::PHI:
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for (const MachineOperand &MO : MI.uses()) {
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if (MO.isReg() && MO.isUse())
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addUsedLanesOnOperand(MO, UsedLanes);
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}
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break;
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return UsedLanes;
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case TargetOpcode::REG_SEQUENCE: {
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// Note: This loop makes the conservative assumption that subregister
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// indices do not overlap or that we do not know how the overlap is
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// resolved when lowering to copies.
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for (unsigned I = 1, N = MI.getNumOperands(); I < N; I += 2) {
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const MachineOperand &MO = MI.getOperand(I);
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unsigned SubIdx = MI.getOperand(I + 1).getImm();
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LaneBitmask MOUsedLanes =
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TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
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addUsedLanesOnOperand(MO, MOUsedLanes);
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}
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break;
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assert(OpNum % 2 == 1);
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unsigned SubIdx = MI.getOperand(OpNum + 1).getImm();
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return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
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}
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case TargetOpcode::INSERT_SUBREG: {
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const MachineOperand &MO2 = MI.getOperand(2);
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unsigned SubIdx = MI.getOperand(3).getImm();
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LaneBitmask MO2UsedLanes =
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TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
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addUsedLanesOnOperand(MO2, MO2UsedLanes);
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if (OpNum == 2)
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return MO2UsedLanes;
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const MachineOperand &MO1 = MI.getOperand(1);
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const MachineOperand &Def = MI.getOperand(0);
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unsigned DefReg = Def.getReg();
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const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
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LaneBitmask MO1UsedLanes;
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@ -241,16 +255,14 @@ void DetectDeadLanes::transferUsedLanesStep(const MachineOperand &Def,
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MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx);
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else
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MO1UsedLanes = RC->LaneMask;
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addUsedLanesOnOperand(MO1, MO1UsedLanes);
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break;
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assert(OpNum == 1);
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return MO1UsedLanes;
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}
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case TargetOpcode::EXTRACT_SUBREG: {
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const MachineOperand &MO = MI.getOperand(1);
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assert(OpNum == 1);
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unsigned SubIdx = MI.getOperand(2).getImm();
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LaneBitmask MOUsedLanes =
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TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes);
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addUsedLanesOnOperand(MO, MOUsedLanes);
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break;
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return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes);
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}
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default:
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llvm_unreachable("function must be called with COPY-like instruction");
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@ -423,6 +435,8 @@ LaneBitmask DetectDeadLanes::determineInitialUsedLanes(unsigned Reg) {
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if (lowersToCopies(UseMI)) {
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const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
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CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO);
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if (CrossCopy)
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DEBUG(dbgs() << "Copy accross incompatible classes: " << UseMI);
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}
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if (!CrossCopy)
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@ -439,6 +453,119 @@ LaneBitmask DetectDeadLanes::determineInitialUsedLanes(unsigned Reg) {
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return UsedLanes;
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}
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bool DetectDeadLanes::isUndefRegAtInput(const MachineOperand &MO,
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const VRegInfo &RegInfo) const {
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unsigned SubReg = MO.getSubReg();
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LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);
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return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask) == 0;
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}
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bool DetectDeadLanes::isUndefInput(const MachineOperand &MO,
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bool *CrossCopy) const {
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if (!MO.isUse())
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return false;
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const MachineInstr &MI = *MO.getParent();
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if (!lowersToCopies(MI))
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return false;
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const MachineOperand &Def = MI.getOperand(0);
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unsigned DefReg = Def.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(DefReg))
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return false;
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unsigned DefRegIdx = TargetRegisterInfo::virtReg2Index(DefReg);
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if (!DefinedByCopy.test(DefRegIdx))
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return false;
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const VRegInfo &DefRegInfo = VRegInfos[DefRegIdx];
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LaneBitmask UsedLanes = transferUsedLanes(MI, DefRegInfo.UsedLanes, MO);
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if (UsedLanes != 0)
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return false;
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unsigned MOReg = MO.getReg();
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if (TargetRegisterInfo::isVirtualRegister(MOReg)) {
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const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
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*CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO);
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}
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return true;
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}
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bool DetectDeadLanes::runOnce(MachineFunction &MF) {
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// First pass: Populate defs/uses of vregs with initial values
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unsigned NumVirtRegs = MRI->getNumVirtRegs();
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for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
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// Determine used/defined lanes and add copy instructions to worklist.
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VRegInfo &Info = VRegInfos[RegIdx];
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Info.DefinedLanes = determineInitialDefinedLanes(Reg);
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Info.UsedLanes = determineInitialUsedLanes(Reg);
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}
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// Iterate as long as defined lanes/used lanes keep changing.
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while (!Worklist.empty()) {
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unsigned RegIdx = Worklist.front();
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Worklist.pop_front();
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WorklistMembers.reset(RegIdx);
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VRegInfo &Info = VRegInfos[RegIdx];
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unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
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// Transfer UsedLanes to operands of DefMI (backwards dataflow).
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MachineOperand &Def = *MRI->def_begin(Reg);
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const MachineInstr &MI = *Def.getParent();
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transferUsedLanesStep(MI, Info.UsedLanes);
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// Transfer DefinedLanes to users of Reg (forward dataflow).
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for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg))
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transferDefinedLanesStep(MO, Info.DefinedLanes);
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}
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DEBUG(
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dbgs() << "Defined/Used lanes:\n";
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for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
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const VRegInfo &Info = VRegInfos[RegIdx];
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dbgs() << PrintReg(Reg, nullptr)
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<< " Used: " << PrintLaneMask(Info.UsedLanes)
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<< " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n';
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}
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dbgs() << "\n";
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);
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bool Again = false;
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// Mark operands as dead/unused.
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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for (MachineOperand &MO : MI.operands()) {
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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continue;
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unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg);
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const VRegInfo &RegInfo = VRegInfos[RegIdx];
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if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes == 0) {
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DEBUG(dbgs() << "Marking operand '" << MO << "' as dead in " << MI);
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MO.setIsDead();
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}
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if (MO.readsReg()) {
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bool CrossCopy = false;
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if (isUndefRegAtInput(MO, RegInfo)) {
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DEBUG(dbgs() << "Marking operand '" << MO << "' as undef in "
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<< MI);
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MO.setIsUndef();
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} else if (isUndefInput(MO, &CrossCopy)) {
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DEBUG(dbgs() << "Marking operand '" << MO << "' as undef in "
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<< MI);
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MO.setIsUndef();
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if (CrossCopy)
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Again = true;
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}
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}
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}
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}
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}
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return Again;
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}
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bool DetectDeadLanes::runOnMachineFunction(MachineFunction &MF) {
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// Don't bother if we won't track subregister liveness later. This pass is
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// required for correctness if subregister liveness is enabled because the
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@ -458,69 +585,10 @@ bool DetectDeadLanes::runOnMachineFunction(MachineFunction &MF) {
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WorklistMembers.resize(NumVirtRegs);
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DefinedByCopy.resize(NumVirtRegs);
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// First pass: Populate defs/uses of vregs with initial values
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for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
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// Determine used/defined lanes and add copy instructions to worklist.
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VRegInfo &Info = VRegInfos[RegIdx];
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Info.DefinedLanes = determineInitialDefinedLanes(Reg);
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Info.UsedLanes = determineInitialUsedLanes(Reg);
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}
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// Iterate as long as defined lanes/used lanes keep changing.
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while (!Worklist.empty()) {
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unsigned RegIdx = Worklist.front();
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Worklist.pop_front();
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WorklistMembers.reset(RegIdx);
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VRegInfo &Info = VRegInfos[RegIdx];
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unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
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// Transfer UsedLanes to operands of DefMI (backwards dataflow).
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MachineOperand &Def = *MRI->def_begin(Reg);
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transferUsedLanesStep(Def, Info.UsedLanes);
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// Transfer DefinedLanes to users of Reg (forward dataflow).
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for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg))
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transferDefinedLanesStep(MO, Info.DefinedLanes);
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}
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DEBUG(
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dbgs() << "Defined/Used lanes:\n";
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for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
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const VRegInfo &Info = VRegInfos[RegIdx];
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dbgs() << PrintReg(Reg, nullptr)
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<< " Used: " << PrintLaneMask(Info.UsedLanes)
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<< " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n';
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}
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dbgs() << "\n";
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);
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// Mark operands as dead/unused.
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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for (MachineOperand &MO : MI.operands()) {
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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continue;
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unsigned SubReg = MO.getSubReg();
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LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);
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unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg);
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const VRegInfo &RegInfo = VRegInfos[RegIdx];
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if (RegInfo.UsedLanes == 0 && MO.isDef() && !MO.isDead()) {
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DEBUG(dbgs() << "Marking operand '" << MO << "' as dead in " << MI);
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MO.setIsDead();
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}
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if (((RegInfo.UsedLanes & Mask) == 0 ||
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(RegInfo.DefinedLanes & Mask) == 0) && MO.readsReg()) {
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DEBUG(dbgs() << "Marking operand '" << MO << "' as undef in " << MI);
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MO.setIsUndef();
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}
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}
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}
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}
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bool Again;
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do {
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Again = runOnce(MF);
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} while(Again);
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DefinedByCopy.clear();
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WorklistMembers.clear();
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@ -5,6 +5,7 @@
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define void @test2() { ret void }
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define void @test3() { ret void }
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define void @test4() { ret void }
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define void @test5() { ret void }
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define void @loop0() { ret void }
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define void @loop1() { ret void }
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define void @loop2() { ret void }
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@ -20,7 +21,7 @@
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# CHECK: S_NOP 0, implicit %3:sub1
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# CHECK: S_NOP 0, implicit undef %3:sub2
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# CHECK: %4 = COPY %3:sub0_sub1
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# CHECK: %5 = COPY %3:sub2_sub3
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# CHECK: %5 = COPY undef %3:sub2_sub3
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# CHECK: S_NOP 0, implicit %4:sub0
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# CHECK: S_NOP 0, implicit %4:sub1
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# CHECK: S_NOP 0, implicit undef %5:sub0
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@ -255,6 +256,25 @@ body: |
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S_NOP 0, implicit %1
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...
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---
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# Check that unused inputs are marked as undef, even if the vreg itself is
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# used.
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# CHECK-LABEL: name: test5
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# CHECK: S_NOP 0, implicit-def %0
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# CHECK: %1 = REG_SEQUENCE undef %0, {{[0-9]+}}, %0, {{[0-9]+}}
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# CHECK: S_NOP 0, implicit %1:sub1
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name: test5
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isSSA: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sreg_32 }
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- { id: 1, class: sreg_64 }
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body: |
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bb.0:
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S_NOP 0, implicit-def %0
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%1 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1
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S_NOP 0, implicit %1:sub1
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...
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---
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# Check "optimistic" dataflow fixpoint in phi-loops.
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# CHECK-LABEL: name: loop0
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# CHECK: bb.0:
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@ -6,10 +6,10 @@ target triple="amdgcn--"
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; CHECK-LABEL: foobar:
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; CHECK: s_load_dword s2, s[0:1], 0x9
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; CHECK-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb
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; CHECK-NEXT: v_mbcnt_lo_u32_b32_e64
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; CHECK-NEXT: v_cmp_eq_i32_e32 vcc, 0, v0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK: s_and_saveexec_b64 s[2:3], vcc
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; CHECK: v_mbcnt_lo_u32_b32_e64
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; CHECK-NEXT: v_cmp_eq_i32_e32 vcc, 0, v0
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; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc
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; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
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; BB0_1:
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; CHECK: s_load_dword s0, s[0:1], 0xa
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