Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT.
This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
This commit is contained in:
Owen Anderson
parent
cb6eb82e48
commit
21b1788ad0
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@ -55,16 +55,13 @@ namespace {
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MachineVerifier(Pass *pass, const char *b) :
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PASS(pass),
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Banner(b),
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OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
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Banner(b)
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{}
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bool runOnMachineFunction(MachineFunction &MF);
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Pass *const PASS;
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const char *Banner;
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const char *const OutFileName;
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raw_ostream *OS;
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const MachineFunction *MF;
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const TargetMachine *TM;
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const TargetInstrInfo *TII;
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@ -277,22 +274,6 @@ void MachineFunction::verify(Pass *p, const char *Banner) const {
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}
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bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
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raw_ostream *OutFile = nullptr;
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if (OutFileName) {
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std::error_code EC;
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OutFile = new raw_fd_ostream(OutFileName, EC,
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sys::fs::F_Append | sys::fs::F_Text);
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if (EC) {
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errs() << "Error opening '" << OutFileName << "': " << EC.message()
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<< '\n';
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exit(1);
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}
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OS = OutFile;
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} else {
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OS = &errs();
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}
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foundErrors = 0;
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this->MF = &MF;
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@ -327,7 +308,7 @@ bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
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MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
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if (MBBI->getParent() != MFI) {
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report("Bad instruction parent pointer", MFI);
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*OS << "Instruction: " << *MBBI;
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errs() << "Instruction: " << *MBBI;
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continue;
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}
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@ -363,9 +344,7 @@ bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
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}
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visitMachineFunctionAfter();
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if (OutFile)
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delete OutFile;
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else if (foundErrors)
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if (foundErrors)
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report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
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// Clean up.
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@ -382,76 +361,76 @@ bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
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void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
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assert(MF);
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*OS << '\n';
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errs() << '\n';
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if (!foundErrors++) {
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if (Banner)
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*OS << "# " << Banner << '\n';
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MF->print(*OS, Indexes);
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errs() << "# " << Banner << '\n';
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MF->print(errs(), Indexes);
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}
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*OS << "*** Bad machine code: " << msg << " ***\n"
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errs() << "*** Bad machine code: " << msg << " ***\n"
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<< "- function: " << MF->getName() << "\n";
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}
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void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
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assert(MBB);
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report(msg, MBB->getParent());
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*OS << "- basic block: BB#" << MBB->getNumber()
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errs() << "- basic block: BB#" << MBB->getNumber()
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<< ' ' << MBB->getName()
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<< " (" << (const void*)MBB << ')';
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if (Indexes)
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*OS << " [" << Indexes->getMBBStartIdx(MBB)
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errs() << " [" << Indexes->getMBBStartIdx(MBB)
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<< ';' << Indexes->getMBBEndIdx(MBB) << ')';
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*OS << '\n';
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errs() << '\n';
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}
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void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
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assert(MI);
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report(msg, MI->getParent());
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*OS << "- instruction: ";
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errs() << "- instruction: ";
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if (Indexes && Indexes->hasIndex(MI))
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*OS << Indexes->getInstructionIndex(MI) << '\t';
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MI->print(*OS, TM);
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errs() << Indexes->getInstructionIndex(MI) << '\t';
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MI->print(errs(), TM);
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}
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void MachineVerifier::report(const char *msg,
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const MachineOperand *MO, unsigned MONum) {
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assert(MO);
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report(msg, MO->getParent());
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*OS << "- operand " << MONum << ": ";
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MO->print(*OS, TM);
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*OS << "\n";
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errs() << "- operand " << MONum << ": ";
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MO->print(errs(), TM);
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errs() << "\n";
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}
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void MachineVerifier::report(const char *msg, const MachineFunction *MF,
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const LiveInterval &LI) {
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report(msg, MF);
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*OS << "- interval: " << LI << '\n';
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errs() << "- interval: " << LI << '\n';
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}
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void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
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const LiveInterval &LI) {
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report(msg, MBB);
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*OS << "- interval: " << LI << '\n';
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errs() << "- interval: " << LI << '\n';
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}
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void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
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const LiveRange &LR, unsigned Reg,
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unsigned LaneMask) {
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report(msg, MBB);
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*OS << "- liverange: " << LR << '\n';
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*OS << "- register: " << PrintReg(Reg, TRI) << '\n';
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errs() << "- liverange: " << LR << '\n';
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errs() << "- register: " << PrintReg(Reg, TRI) << '\n';
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if (LaneMask != 0)
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*OS << "- lanemask: " << format("%04X\n", LaneMask);
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errs() << "- lanemask: " << format("%04X\n", LaneMask);
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}
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void MachineVerifier::report(const char *msg, const MachineFunction *MF,
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const LiveRange &LR, unsigned Reg,
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unsigned LaneMask) {
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report(msg, MF);
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*OS << "- liverange: " << LR << '\n';
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*OS << "- register: " << PrintReg(Reg, TRI) << '\n';
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errs() << "- liverange: " << LR << '\n';
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errs() << "- register: " << PrintReg(Reg, TRI) << '\n';
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if (LaneMask != 0)
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*OS << "- lanemask: " << format("%04X\n", LaneMask);
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errs() << "- lanemask: " << format("%04X\n", LaneMask);
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}
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void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
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@ -539,7 +518,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
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report("MBB has successor that isn't part of the function.", MBB);
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if (!MBBInfoMap[*I].Preds.count(MBB)) {
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report("Inconsistent CFG", MBB);
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*OS << "MBB is not in the predecessor list of the successor BB#"
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errs() << "MBB is not in the predecessor list of the successor BB#"
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<< (*I)->getNumber() << ".\n";
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}
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}
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@ -551,7 +530,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
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report("MBB has predecessor that isn't part of the function.", MBB);
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if (!MBBInfoMap[*I].Succs.count(MBB)) {
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report("Inconsistent CFG", MBB);
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*OS << "MBB is not in the successor list of the predecessor BB#"
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errs() << "MBB is not in the successor list of the predecessor BB#"
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<< (*I)->getNumber() << ".\n";
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}
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}
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@ -726,7 +705,7 @@ void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
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SlotIndex idx = Indexes->getInstructionIndex(MI);
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if (!(idx > lastIndex)) {
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report("Instruction index out of order", MI);
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*OS << "Last instruction was at " << lastIndex << '\n';
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errs() << "Last instruction was at " << lastIndex << '\n';
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}
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lastIndex = idx;
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}
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@ -739,7 +718,7 @@ void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
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FirstTerminator = MI;
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} else if (FirstTerminator) {
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report("Non-terminator instruction after the first terminator", MI);
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*OS << "First terminator was:\t" << *FirstTerminator;
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errs() << "First terminator was:\t" << *FirstTerminator;
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}
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}
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@ -791,7 +770,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
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const MCInstrDesc &MCID = MI->getDesc();
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if (MI->getNumOperands() < MCID.getNumOperands()) {
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report("Too few operands", MI);
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*OS << MCID.getNumOperands() << " operands expected, but "
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errs() << MCID.getNumOperands() << " operands expected, but "
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<< MI->getNumOperands() << " given.\n";
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}
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@ -921,7 +900,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
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TII->getRegClass(MCID, MONum, TRI, *MF)) {
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if (!DRC->contains(Reg)) {
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report("Illegal physical register for instruction", MO, MONum);
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*OS << TRI->getName(Reg) << " is not a "
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errs() << TRI->getName(Reg) << " is not a "
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<< TRI->getRegClassName(DRC) << " register.\n";
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}
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}
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@ -933,13 +912,13 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
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TRI->getSubClassWithSubReg(RC, SubIdx);
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if (!SRC) {
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report("Invalid subregister index for virtual register", MO, MONum);
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*OS << "Register class " << TRI->getRegClassName(RC)
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errs() << "Register class " << TRI->getRegClassName(RC)
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<< " does not support subreg index " << SubIdx << "\n";
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return;
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}
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if (RC != SRC) {
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report("Invalid register class for subregister index", MO, MONum);
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*OS << "Register class " << TRI->getRegClassName(RC)
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errs() << "Register class " << TRI->getRegClassName(RC)
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<< " does not fully support subreg index " << SubIdx << "\n";
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return;
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}
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@ -961,7 +940,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
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}
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if (!RC->hasSuperClassEq(DRC)) {
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report("Illegal virtual register for instruction", MO, MONum);
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*OS << "Expected a " << TRI->getRegClassName(DRC)
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errs() << "Expected a " << TRI->getRegClassName(DRC)
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<< " register, but got a " << TRI->getRegClassName(RC)
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<< " register\n";
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}
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@ -987,11 +966,11 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
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SlotIndex Idx = LiveInts->getInstructionIndex(MI);
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if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
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report("Instruction loads from dead spill slot", MO, MONum);
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*OS << "Live stack: " << LI << '\n';
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errs() << "Live stack: " << LI << '\n';
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}
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if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) {
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report("Instruction stores to dead spill slot", MO, MONum);
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*OS << "Live stack: " << LI << '\n';
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errs() << "Live stack: " << LI << '\n';
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}
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}
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break;
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@ -1030,12 +1009,12 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
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LiveQueryResult LRQ = LR->Query(UseIdx);
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if (!LRQ.valueIn()) {
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report("No live segment at use", MO, MONum);
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*OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
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errs() << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
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<< ' ' << *LR << '\n';
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}
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if (MO->isKill() && !LRQ.isKill()) {
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report("Live range continues after kill flag", MO, MONum);
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*OS << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n';
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errs() << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n';
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}
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}
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}
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@ -1048,13 +1027,13 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
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LiveQueryResult LRQ = LI.Query(UseIdx);
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if (!LRQ.valueIn()) {
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report("No live segment at use", MO, MONum);
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*OS << UseIdx << " is not live in " << LI << '\n';
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errs() << UseIdx << " is not live in " << LI << '\n';
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}
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// Check for extra kill flags.
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// Note that we allow missing kill flags for now.
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if (MO->isKill() && !LRQ.isKill()) {
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report("Live range continues after kill flag", MO, MONum);
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*OS << "Live range: " << LI << '\n';
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errs() << "Live range: " << LI << '\n';
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}
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} else {
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report("Virtual register has no live interval", MO, MONum);
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@ -1137,19 +1116,19 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
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assert(VNI && "NULL valno is not allowed");
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if (VNI->def != DefIdx) {
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report("Inconsistent valno->def", MO, MONum);
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*OS << "Valno " << VNI->id << " is not defined at "
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errs() << "Valno " << VNI->id << " is not defined at "
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<< DefIdx << " in " << LI << '\n';
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}
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} else {
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report("No live segment at def", MO, MONum);
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*OS << DefIdx << " is not live in " << LI << '\n';
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errs() << DefIdx << " is not live in " << LI << '\n';
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}
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// Check that, if the dead def flag is present, LiveInts agree.
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if (MO->isDead()) {
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LiveQueryResult LRQ = LI.Query(DefIdx);
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if (!LRQ.isDeadDef()) {
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report("Live range continues after dead def flag", MO, MONum);
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*OS << "Live range: " << LI << '\n';
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errs() << "Live range: " << LI << '\n';
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}
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}
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} else {
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@ -1191,7 +1170,7 @@ MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
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SlotIndex stop = Indexes->getMBBEndIdx(MBB);
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if (!(stop > lastIndex)) {
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report("Block ends before last instruction index", MBB);
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*OS << "Block ends at " << stop
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errs() << "Block ends at " << stop
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<< " last instruction was at " << lastIndex << '\n';
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}
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lastIndex = stop;
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@ -1293,7 +1272,7 @@ void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
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PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
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if (!seen.count(*PrI)) {
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report("Missing PHI operand", &BBI);
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*OS << "BB#" << (*PrI)->getNumber()
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errs() << "BB#" << (*PrI)->getNumber()
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<< " is a predecessor according to the CFG.\n";
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}
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}
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@ -1324,7 +1303,7 @@ void MachineVerifier::visitMachineFunctionAfter() {
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++I)
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if (MInfo.regsKilled.count(*I)) {
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report("Virtual register killed in block, but needed live out.", &MBB);
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*OS << "Virtual register " << PrintReg(*I)
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errs() << "Virtual register " << PrintReg(*I)
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<< " is used after the block.\n";
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}
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}
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@ -1356,13 +1335,13 @@ void MachineVerifier::verifyLiveVariables() {
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if (MInfo.vregsRequired.count(Reg)) {
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if (!VI.AliveBlocks.test(MBB.getNumber())) {
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report("LiveVariables: Block missing from AliveBlocks", &MBB);
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*OS << "Virtual register " << PrintReg(Reg)
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errs() << "Virtual register " << PrintReg(Reg)
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<< " must be live through the block.\n";
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}
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} else {
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if (VI.AliveBlocks.test(MBB.getNumber())) {
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report("LiveVariables: Block should not be in AliveBlocks", &MBB);
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*OS << "Virtual register " << PrintReg(Reg)
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errs() << "Virtual register " << PrintReg(Reg)
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<< " is not needed live through the block.\n";
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}
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}
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@ -1381,7 +1360,7 @@ void MachineVerifier::verifyLiveIntervals() {
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if (!LiveInts->hasInterval(Reg)) {
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report("Missing live interval for virtual register", MF);
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*OS << PrintReg(Reg, TRI) << " still has defs or uses\n";
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errs() << PrintReg(Reg, TRI) << " still has defs or uses\n";
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continue;
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}
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@ -1407,13 +1386,13 @@ void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
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if (!DefVNI) {
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report("Valno not live at def and not marked unused", MF, LR, Reg,
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LaneMask);
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*OS << "Valno #" << VNI->id << '\n';
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errs() << "Valno #" << VNI->id << '\n';
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return;
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}
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if (DefVNI != VNI) {
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report("Live segment at def has different valno", MF, LR, Reg, LaneMask);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< " where valno #" << DefVNI->id << " is live\n";
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return;
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}
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@ -1421,7 +1400,7 @@ void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
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const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
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if (!MBB) {
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report("Invalid definition index", MF, LR, Reg, LaneMask);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< " in " << LR << '\n';
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return;
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}
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@ -1430,7 +1409,7 @@ void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
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if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
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report("PHIDef value is not defined at MBB start", MBB, LR, Reg,
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LaneMask);
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*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
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errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
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<< ", not at the beginning of BB#" << MBB->getNumber() << '\n';
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}
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return;
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@ -1440,7 +1419,7 @@ void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
|
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const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
|
||||
if (!MI) {
|
||||
report("No instruction at def index", MBB, LR, Reg, LaneMask);
|
||||
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
|
||||
errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1468,7 +1447,7 @@ void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
|
|||
|
||||
if (!hasDef) {
|
||||
report("Defining instruction does not modify register", MI);
|
||||
*OS << "Valno #" << VNI->id << " in " << LR << '\n';
|
||||
errs() << "Valno #" << VNI->id << " in " << LR << '\n';
|
||||
}
|
||||
|
||||
// Early clobber defs begin at USE slots, but other defs must begin at
|
||||
|
|
@ -1477,12 +1456,12 @@ void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
|
|||
if (!VNI->def.isEarlyClobber()) {
|
||||
report("Early clobber def must be at an early-clobber slot", MBB, LR,
|
||||
Reg, LaneMask);
|
||||
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
|
||||
errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
|
||||
}
|
||||
} else if (!VNI->def.isRegister()) {
|
||||
report("Non-PHI, non-early clobber def must be at a register slot",
|
||||
MBB, LR, Reg, LaneMask);
|
||||
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
|
||||
errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1496,32 +1475,32 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
|
|||
|
||||
if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
|
||||
report("Foreign valno in live segment", MF, LR, Reg, LaneMask);
|
||||
*OS << S << " has a bad valno\n";
|
||||
errs() << S << " has a bad valno\n";
|
||||
}
|
||||
|
||||
if (VNI->isUnused()) {
|
||||
report("Live segment valno is marked unused", MF, LR, Reg, LaneMask);
|
||||
*OS << S << '\n';
|
||||
errs() << S << '\n';
|
||||
}
|
||||
|
||||
const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
|
||||
if (!MBB) {
|
||||
report("Bad start of live segment, no basic block", MF, LR, Reg, LaneMask);
|
||||
*OS << S << '\n';
|
||||
errs() << S << '\n';
|
||||
return;
|
||||
}
|
||||
SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
|
||||
if (S.start != MBBStartIdx && S.start != VNI->def) {
|
||||
report("Live segment must begin at MBB entry or valno def", MBB, LR, Reg,
|
||||
LaneMask);
|
||||
*OS << S << '\n';
|
||||
errs() << S << '\n';
|
||||
}
|
||||
|
||||
const MachineBasicBlock *EndMBB =
|
||||
LiveInts->getMBBFromIndex(S.end.getPrevSlot());
|
||||
if (!EndMBB) {
|
||||
report("Bad end of live segment, no basic block", MF, LR, Reg, LaneMask);
|
||||
*OS << S << '\n';
|
||||
errs() << S << '\n';
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1540,7 +1519,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
|
|||
if (!MI) {
|
||||
report("Live segment doesn't end at a valid instruction", EndMBB, LR, Reg,
|
||||
LaneMask);
|
||||
*OS << S << '\n';
|
||||
errs() << S << '\n';
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1548,7 +1527,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
|
|||
if (S.end.isBlock()) {
|
||||
report("Live segment ends at B slot of an instruction", EndMBB, LR, Reg,
|
||||
LaneMask);
|
||||
*OS << S << '\n';
|
||||
errs() << S << '\n';
|
||||
}
|
||||
|
||||
if (S.end.isDead()) {
|
||||
|
|
@ -1557,7 +1536,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
|
|||
if (!SlotIndex::isSameInstr(S.start, S.end)) {
|
||||
report("Live segment ending at dead slot spans instructions", EndMBB, LR,
|
||||
Reg, LaneMask);
|
||||
*OS << S << '\n';
|
||||
errs() << S << '\n';
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1568,7 +1547,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
|
|||
report("Live segment ending at early clobber slot must be "
|
||||
"redefined by an EC def in the same instruction", EndMBB, LR, Reg,
|
||||
LaneMask);
|
||||
*OS << S << '\n';
|
||||
errs() << S << '\n';
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1597,7 +1576,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
|
|||
if (!MRI->tracksSubRegLiveness() || LaneMask != 0 || !hasSubRegDef) {
|
||||
report("Instruction ending live segment doesn't read the register",
|
||||
MI);
|
||||
*OS << S << " in " << LR << '\n';
|
||||
errs() << S << " in " << LR << '\n';
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1638,7 +1617,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
|
|||
if (!PVNI) {
|
||||
report("Register not marked live out of predecessor", *PI, LR, Reg,
|
||||
LaneMask);
|
||||
*OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
|
||||
errs() << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
|
||||
<< '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
|
||||
<< PEnd << '\n';
|
||||
continue;
|
||||
|
|
@ -1648,7 +1627,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
|
|||
if (!IsPHI && PVNI != VNI) {
|
||||
report("Different value live out of predecessor", *PI, LR, Reg,
|
||||
LaneMask);
|
||||
*OS << "Valno #" << PVNI->id << " live out of BB#"
|
||||
errs() << "Valno #" << PVNI->id << " live out of BB#"
|
||||
<< (*PI)->getNumber() << '@' << PEnd
|
||||
<< "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
|
||||
<< '@' << LiveInts->getMBBStartIdx(MFI) << '\n';
|
||||
|
|
@ -1697,12 +1676,12 @@ void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
|
|||
if (NumComp > 1) {
|
||||
report("Multiple connected components in live interval", MF, LI);
|
||||
for (unsigned comp = 0; comp != NumComp; ++comp) {
|
||||
*OS << comp << ": valnos";
|
||||
errs() << comp << ": valnos";
|
||||
for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
|
||||
E = LI.vni_end(); I!=E; ++I)
|
||||
if (comp == ConEQ.getEqClass(*I))
|
||||
*OS << ' ' << (*I)->id;
|
||||
*OS << '\n';
|
||||
errs() << ' ' << (*I)->id;
|
||||
errs() << '\n';
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1783,7 +1762,7 @@ void MachineVerifier::verifyStackFrame() {
|
|||
BBState.ExitValue;
|
||||
if (BBState.ExitIsSetup && AbsSPAdj != Size) {
|
||||
report("FrameDestroy <n> is after FrameSetup <m>", &I);
|
||||
*OS << "FrameDestroy <" << Size << "> is after FrameSetup <"
|
||||
errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
|
||||
<< AbsSPAdj << ">.\n";
|
||||
}
|
||||
BBState.ExitValue += Size;
|
||||
|
|
@ -1800,7 +1779,7 @@ void MachineVerifier::verifyStackFrame() {
|
|||
(SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
|
||||
SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
|
||||
report("The exit stack state of a predecessor is inconsistent.", MBB);
|
||||
*OS << "Predecessor BB#" << (*I)->getNumber() << " has exit state ("
|
||||
errs() << "Predecessor BB#" << (*I)->getNumber() << " has exit state ("
|
||||
<< SPState[(*I)->getNumber()].ExitValue << ", "
|
||||
<< SPState[(*I)->getNumber()].ExitIsSetup
|
||||
<< "), while BB#" << MBB->getNumber() << " has entry state ("
|
||||
|
|
@ -1816,7 +1795,7 @@ void MachineVerifier::verifyStackFrame() {
|
|||
(SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
|
||||
SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
|
||||
report("The entry stack state of a successor is inconsistent.", MBB);
|
||||
*OS << "Successor BB#" << (*I)->getNumber() << " has entry state ("
|
||||
errs() << "Successor BB#" << (*I)->getNumber() << " has entry state ("
|
||||
<< SPState[(*I)->getNumber()].EntryValue << ", "
|
||||
<< SPState[(*I)->getNumber()].EntryIsSetup
|
||||
<< "), while BB#" << MBB->getNumber() << " has exit state ("
|
||||
|
|
|
|||
|
|
@ -81,7 +81,9 @@ static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
|
|||
cl::desc("Dump garbage collector data"));
|
||||
static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
|
||||
cl::desc("Verify generated machine code"),
|
||||
cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=nullptr));
|
||||
cl::init(false),
|
||||
cl::ZeroOrMore);
|
||||
|
||||
static cl::opt<std::string>
|
||||
PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
|
||||
cl::desc("Print machine instrs"),
|
||||
|
|
|
|||
|
|
@ -270,6 +270,10 @@ for pattern in [r"\bbugpoint\b(?!-)",
|
|||
# Warn, but still provide a substitution.
|
||||
lit_config.note('Did not find ' + tool_name + ' in ' + llvm_tools_dir)
|
||||
tool_path = llvm_tools_dir + '/' + tool_name
|
||||
if (tool_name == "llc" and
|
||||
'LLVM_ENABLE_MACHINE_VERIFIER' in os.environ and
|
||||
os.environ['LLVM_ENABLE_MACHINE_VERIFIER'] == "1"):
|
||||
tool_path += " -verify-machineinstrs"
|
||||
config.substitutions.append((pattern, tool_pipe + tool_path))
|
||||
|
||||
### Targets
|
||||
|
|
|
|||
Loading…
Reference in New Issue