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[X86] Strip unnecessary WriteFShuffle instruction instrw overrides from scheduler models. 

llvm-svn: 330508
This commit is contained in:
Simon Pilgrim 2018-04-21 14:56:56 +00:00
parent b25187adfb
commit 2193524fb4
4 changed files with 6 additions and 143 deletions
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20
llvm/lib/Target/X86/X86SchedBroadwell.td
View File

@ -356,18 +356,10 @@ def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
"MMX_MOVD64to64rr", "MMX_MOVD64to64rr",
"MMX_MOVQ2DQrr", "MMX_MOVQ2DQrr",
"VBROADCASTSSrr", "VBROADCASTSSrr",
"(V?)INSERTPSrr",
"(V?)MOV64toPQIrr", "(V?)MOV64toPQIrr",
"(V?)MOVAPD(Y?)rr", "(V?)MOVAPD(Y?)rr",
"(V?)MOVAPS(Y?)rr", "(V?)MOVAPS(Y?)rr",
"(V?)MOVDDUP(Y?)rr",
"(V?)MOVDI2PDIrr", "(V?)MOVDI2PDIrr",
"(V?)MOVHLPSrr",
"(V?)MOVLHPSrr",
"(V?)MOVSDrr",
"(V?)MOVSHDUP(Y?)rr",
"(V?)MOVSLDUP(Y?)rr",
"(V?)MOVSSrr",
"(V?)MOVUPD(Y?)rr", "(V?)MOVUPD(Y?)rr",
"(V?)MOVUPS(Y?)rr", "(V?)MOVUPS(Y?)rr",
"(V?)ORPD(Y?)rr", "(V?)ORPD(Y?)rr",
@ -376,8 +368,6 @@ def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
"(V?)PBLENDW(Y?)rri", "(V?)PBLENDW(Y?)rri",
"VPBROADCASTDrr", "VPBROADCASTDrr",
"VPBROADCASTQrr", "VPBROADCASTQrr",
"VPERMILPD(Y?)ri",
"VPERMILPS(Y?)ri",
"(V?)PMOVSXBDrr", "(V?)PMOVSXBDrr",
"(V?)PMOVSXBQrr", "(V?)PMOVSXBQrr",
"(V?)PMOVSXBWrr", "(V?)PMOVSXBWrr",
@ -402,13 +392,7 @@ def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
"(V?)PUNPCKLBW(Y?)rr", "(V?)PUNPCKLBW(Y?)rr",
"(V?)PUNPCKLDQ(Y?)rr", "(V?)PUNPCKLDQ(Y?)rr",
"(V?)PUNPCKLQDQ(Y?)rr", "(V?)PUNPCKLQDQ(Y?)rr",
"(V?)PUNPCKLWD(Y?)rr", "(V?)PUNPCKLWD(Y?)rr")>;
"(V?)SHUFPD(Y?)rri",
"(V?)SHUFPS(Y?)rri",
"(V?)UNPCKHPD(Y?)rr",
"(V?)UNPCKHPS(Y?)rr",
"(V?)UNPCKLPD(Y?)rr",
"(V?)UNPCKLPS(Y?)rr")>;
def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> { def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
let Latency = 1; let Latency = 1;
@ -508,8 +492,6 @@ def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr", def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr",
"(V?)BLENDPD(Y?)rri",
"(V?)BLENDPS(Y?)rri",
"(V?)MOVDQA(Y?)rr", "(V?)MOVDQA(Y?)rr",
"(V?)MOVDQU(Y?)rr", "(V?)MOVDQU(Y?)rr",
"(V?)MOVPQI2QIrr", "(V?)MOVPQI2QIrr",

20
llvm/lib/Target/X86/X86SchedHaswell.td
View File

@ -707,18 +707,10 @@ def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr",
"MMX_MOVD64to64rr", "MMX_MOVD64to64rr",
"MMX_MOVQ2DQrr", "MMX_MOVQ2DQrr",
"VBROADCASTSSrr", "VBROADCASTSSrr",
"(V?)INSERTPSrr",
"(V?)MOV64toPQIrr", "(V?)MOV64toPQIrr",
"(V?)MOVAPD(Y?)rr", "(V?)MOVAPD(Y?)rr",
"(V?)MOVAPS(Y?)rr", "(V?)MOVAPS(Y?)rr",
"(V?)MOVDDUP(Y?)rr",
"(V?)MOVDI2PDIrr", "(V?)MOVDI2PDIrr",
"(V?)MOVHLPSrr",
"(V?)MOVLHPSrr",
"(V?)MOVSDrr",
"(V?)MOVSHDUP(Y?)rr",
"(V?)MOVSLDUP(Y?)rr",
"(V?)MOVSSrr",
"(V?)MOVUPD(Y?)rr", "(V?)MOVUPD(Y?)rr",
"(V?)MOVUPS(Y?)rr", "(V?)MOVUPS(Y?)rr",
"(V?)PACKSSDW(Y?)rr", "(V?)PACKSSDW(Y?)rr",
@ -729,8 +721,6 @@ def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr",
"(V?)PBLENDW(Y?)rri", "(V?)PBLENDW(Y?)rri",
"VPBROADCASTDrr", "VPBROADCASTDrr",
"VPBROADCASTQrr", "VPBROADCASTQrr",
"VPERMILPD(Y?)ri",
"VPERMILPS(Y?)ri",
"(V?)PMOVSXBDrr", "(V?)PMOVSXBDrr",
"(V?)PMOVSXBQrr", "(V?)PMOVSXBQrr",
"(V?)PMOVSXBWrr", "(V?)PMOVSXBWrr",
@ -755,13 +745,7 @@ def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr",
"(V?)PUNPCKLBW(Y?)rr", "(V?)PUNPCKLBW(Y?)rr",
"(V?)PUNPCKLDQ(Y?)rr", "(V?)PUNPCKLDQ(Y?)rr",
"(V?)PUNPCKLQDQ(Y?)rr", "(V?)PUNPCKLQDQ(Y?)rr",
"(V?)PUNPCKLWD(Y?)rr", "(V?)PUNPCKLWD(Y?)rr")>;
"(V?)SHUFPD(Y?)rri",
"(V?)SHUFPS(Y?)rri",
"(V?)UNPCKHPD(Y?)rr",
"(V?)UNPCKHPS(Y?)rr",
"(V?)UNPCKLPD(Y?)rr",
"(V?)UNPCKLPS(Y?)rr")>;
def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> { def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> {
let Latency = 1; let Latency = 1;
@ -863,8 +847,6 @@ def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVQ64rr", def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVQ64rr",
"(V?)BLENDPD(Y?)rri",
"(V?)BLENDPS(Y?)rri",
"(V?)MOVDQA(Y?)rr", "(V?)MOVDQA(Y?)rr",
"(V?)MOVDQU(Y?)rr", "(V?)MOVDQU(Y?)rr",
"(V?)MOVPQI2QIrr", "(V?)MOVPQI2QIrr",

22
llvm/lib/Target/X86/X86SchedSkylakeClient.td
View File

@ -359,16 +359,8 @@ def: InstRW<[SKLWriteResGroup3], (instregex "COMP_FST0r",
"UCOM_FPr", "UCOM_FPr",
"UCOM_Fr", "UCOM_Fr",
"VBROADCASTSSrr", "VBROADCASTSSrr",
"(V?)INSERTPSrr",
"(V?)MOV64toPQIrr", "(V?)MOV64toPQIrr",
"(V?)MOVDDUP(Y?)rr",
"(V?)MOVDI2PDIrr", "(V?)MOVDI2PDIrr",
"(V?)MOVHLPSrr",
"(V?)MOVLHPSrr",
"(V?)MOVSDrr",
"(V?)MOVSHDUP(Y?)rr",
"(V?)MOVSLDUP(Y?)rr",
"(V?)MOVSSrr",
"(V?)PACKSSDW(Y?)rr", "(V?)PACKSSDW(Y?)rr",
"(V?)PACKSSWB(Y?)rr", "(V?)PACKSSWB(Y?)rr",
"(V?)PACKUSDW(Y?)rr", "(V?)PACKUSDW(Y?)rr",
@ -377,8 +369,6 @@ def: InstRW<[SKLWriteResGroup3], (instregex "COMP_FST0r",
"(V?)PBLENDW(Y?)rri", "(V?)PBLENDW(Y?)rri",
"VPBROADCASTDrr", "VPBROADCASTDrr",
"VPBROADCASTQrr", "VPBROADCASTQrr",
"VPERMILPD(Y?)ri",
"VPERMILPS(Y?)ri",
"(V?)PMOVSXBDrr", "(V?)PMOVSXBDrr",
"(V?)PMOVSXBQrr", "(V?)PMOVSXBQrr",
"(V?)PMOVSXBWrr", "(V?)PMOVSXBWrr",
@ -403,13 +393,7 @@ def: InstRW<[SKLWriteResGroup3], (instregex "COMP_FST0r",
"(V?)PUNPCKLBW(Y?)rr", "(V?)PUNPCKLBW(Y?)rr",
"(V?)PUNPCKLDQ(Y?)rr", "(V?)PUNPCKLDQ(Y?)rr",
"(V?)PUNPCKLQDQ(Y?)rr", "(V?)PUNPCKLQDQ(Y?)rr",
"(V?)PUNPCKLWD(Y?)rr", "(V?)PUNPCKLWD(Y?)rr")>;
"(V?)SHUFPD(Y?)rri",
"(V?)SHUFPS(Y?)rri",
"(V?)UNPCKHPD(Y?)rr",
"(V?)UNPCKHPS(Y?)rr",
"(V?)UNPCKLPD(Y?)rr",
"(V?)UNPCKLPS(Y?)rr")>;
def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> { def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
let Latency = 1; let Latency = 1;
@ -540,9 +524,7 @@ def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SKLWriteResGroup9], (instregex "(V?)BLENDPD(Y?)rri", def: InstRW<[SKLWriteResGroup9], (instregex "(V?)MOVAPD(Y?)rr",
"(V?)BLENDPS(Y?)rri",
"(V?)MOVAPD(Y?)rr",
"(V?)MOVAPS(Y?)rr", "(V?)MOVAPS(Y?)rr",
"(V?)MOVDQA(Y?)rr", "(V?)MOVDQA(Y?)rr",
"(V?)MOVDQU(Y?)rr", "(V?)MOVDQU(Y?)rr",

87
llvm/lib/Target/X86/X86SchedSkylakeServer.td
View File

@ -401,14 +401,7 @@ def: InstRW<[SKXWriteResGroup3], (instregex "COMP_FST0r",
"MMX_MOVD64rr", "MMX_MOVD64rr",
"MMX_MOVD64to64rr", "MMX_MOVD64to64rr",
"MOV64toPQIrr", "MOV64toPQIrr",
"MOVDDUPrr",
"MOVDI2PDIrr", "MOVDI2PDIrr",
"MOVHLPSrr",
"MOVLHPSrr",
"MOVSDrr",
"MOVSHDUPrr",
"MOVSLDUPrr",
"MOVSSrr",
"PACKSSDWrr", "PACKSSDWrr",
"PACKSSWBrr", "PACKSSWBrr",
"PACKUSDWrr", "PACKUSDWrr",
@ -440,44 +433,14 @@ def: InstRW<[SKXWriteResGroup3], (instregex "COMP_FST0r",
"PUNPCKLDQrr", "PUNPCKLDQrr",
"PUNPCKLQDQrr", "PUNPCKLQDQrr",
"PUNPCKLWDrr", "PUNPCKLWDrr",
"SHUFPDrri",
"SHUFPSrri",
"UCOM_FPr", "UCOM_FPr",
"UCOM_Fr", "UCOM_Fr",
"UNPCKHPDrr",
"UNPCKHPSrr",
"UNPCKLPDrr",
"UNPCKLPSrr",
"VBROADCASTI32X2Z128r", "VBROADCASTI32X2Z128r",
"VBROADCASTSSrr", "VBROADCASTSSrr",
"(V?)INSERTPS(Z?)rr",
"VMOV64toPQIZrr", "VMOV64toPQIZrr",
"VMOV64toPQIrr", "VMOV64toPQIrr",
"VMOVDDUPYrr",
"VMOVDDUPZ128rr",
"VMOVDDUPZ256rr",
"VMOVDDUPZrr",
"VMOVDDUPrr",
"VMOVDI2PDIZrr", "VMOVDI2PDIZrr",
"VMOVDI2PDIrr", "VMOVDI2PDIrr",
"VMOVHLPSZrr",
"VMOVHLPSrr",
"VMOVLHPSZrr",
"VMOVLHPSrr",
"VMOVSDZrr",
"VMOVSDrr",
"VMOVSHDUPYrr",
"VMOVSHDUPZ128rr",
"VMOVSHDUPZ256rr",
"VMOVSHDUPZrr",
"VMOVSHDUPrr",
"VMOVSLDUPYrr",
"VMOVSLDUPZ128rr",
"VMOVSLDUPZ256rr",
"VMOVSLDUPZrr",
"VMOVSLDUPrr",
"VMOVSSZrr",
"VMOVSSrr",
"VPACKSSDWYrr", "VPACKSSDWYrr",
"VPACKSSDWZ128rr", "VPACKSSDWZ128rr",
"VPACKSSDWZ256rr", "VPACKSSDWZ256rr",
@ -507,16 +470,6 @@ def: InstRW<[SKXWriteResGroup3], (instregex "COMP_FST0r",
"VPBLENDWrri", "VPBLENDWrri",
"VPBROADCASTDrr", "VPBROADCASTDrr",
"VPBROADCASTQrr", "VPBROADCASTQrr",
"VPERMILPDYri",
"VPERMILPDZ128ri",
"VPERMILPDZ256ri",
"VPERMILPDZri",
"VPERMILPDri",
"VPERMILPSYri",
"VPERMILPSZ128ri",
"VPERMILPSZ256ri",
"VPERMILPSZri",
"VPERMILPSri",
"VPMOVSXBDrr", "VPMOVSXBDrr",
"VPMOVSXBQrr", "VPMOVSXBQrr",
"VPMOVSXBWrr", "VPMOVSXBWrr",
@ -593,37 +546,7 @@ def: InstRW<[SKXWriteResGroup3], (instregex "COMP_FST0r",
"VPUNPCKLWDZ128rr", "VPUNPCKLWDZ128rr",
"VPUNPCKLWDZ256rr", "VPUNPCKLWDZ256rr",
"VPUNPCKLWDZrr", "VPUNPCKLWDZrr",
"VPUNPCKLWDrr", "VPUNPCKLWDrr")>;
"VSHUFPDYrri",
"VSHUFPDZ128rri",
"VSHUFPDZ256rri",
"VSHUFPDZrri",
"VSHUFPDrri",
"VSHUFPSYrri",
"VSHUFPSZ128rri",
"VSHUFPSZ256rri",
"VSHUFPSZrri",
"VSHUFPSrri",
"VUNPCKHPDYrr",
"VUNPCKHPDZ128rr",
"VUNPCKHPDZ256rr",
"VUNPCKHPDZrr",
"VUNPCKHPDrr",
"VUNPCKHPSYrr",
"VUNPCKHPSZ128rr",
"VUNPCKHPSZ256rr",
"VUNPCKHPSZrr",
"VUNPCKHPSrr",
"VUNPCKLPDYrr",
"VUNPCKLPDZ128rr",
"VUNPCKLPDZ256rr",
"VUNPCKLPDZrr",
"VUNPCKLPDrr",
"VUNPCKLPSYrr",
"VUNPCKLPSZ128rr",
"VUNPCKLPSZ256rr",
"VUNPCKLPSZrr",
"VUNPCKLPSrr")>;
def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> { def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {
let Latency = 1; let Latency = 1;
@ -1001,9 +924,7 @@ def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
let NumMicroOps = 1; let NumMicroOps = 1;
let ResourceCycles = [1]; let ResourceCycles = [1];
} }
def: InstRW<[SKXWriteResGroup9], (instregex "BLENDPDrri", def: InstRW<[SKXWriteResGroup9], (instregex "MOVAPDrr",
"BLENDPSrri",
"MOVAPDrr",
"MOVAPSrr", "MOVAPSrr",
"MOVDQArr", "MOVDQArr",
"MOVDQUrr", "MOVDQUrr",
@ -1024,10 +945,6 @@ def: InstRW<[SKXWriteResGroup9], (instregex "BLENDPDrri",
"VBLENDMPSZ128rr", "VBLENDMPSZ128rr",
"VBLENDMPSZ256rr", "VBLENDMPSZ256rr",
"VBLENDMPSZrr", "VBLENDMPSZrr",
"VBLENDPDYrri",
"VBLENDPDrri",
"VBLENDPSYrri",
"VBLENDPSrri",
"VMOVAPDYrr", "VMOVAPDYrr",
"VMOVAPDZ128rr", "VMOVAPDZ128rr",
"VMOVAPDZ256rr", "VMOVAPDZ256rr",