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[x86] With the stronger canonicalization of shuffles added in r218216, 

the new vector shuffle lowering no longer needs to check both symmetric
forms of UNPCK patterns for v4f64.

llvm-svn: 218217
This commit is contained in:
Chandler Carruth 2014-09-21 13:37:51 +00:00
parent b3125c7522
commit 215037e35d
1 changed files with 0 additions and 4 deletions
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4
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -9257,10 +9257,6 @@ static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
if (isShuffleEquivalent(Mask, 4, 0, 6, 2))
return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
if (isShuffleEquivalent(Mask, 5, 1, 7, 3))
return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
// If we have a single input to the zero element, insert that into V1 if we
// can do so cheaply.