[COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics
Reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul, javed.absar Reviewed By: efriedma Subscribers: dmajor, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53115 llvm-svn: 344765
This commit is contained in:
Mandeep Singh Grang
parent
7c80c3a8e4
commit
2147b1af95
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@ -106,6 +106,8 @@ TARGET_HEADER_BUILTIN(_InterlockedXor64, "LLiLLiD*LLi", "nh", "intrin.h"
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TARGET_HEADER_BUILTIN(_ReadWriteBarrier, "v", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
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TARGET_HEADER_BUILTIN(__getReg, "ULLii", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
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TARGET_HEADER_BUILTIN(_ReadStatusReg, "ii", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
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TARGET_HEADER_BUILTIN(_WriteStatusReg, "vii", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
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#undef BUILTIN
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#undef LANGBUILTIN
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@ -6667,6 +6667,43 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
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return EmitSpecialRegisterBuiltin(*this, E, RegisterType, ValueType, IsRead);
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}
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if (BuiltinID == AArch64::BI_ReadStatusReg ||
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BuiltinID == AArch64::BI_WriteStatusReg) {
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LLVMContext &Context = CGM.getLLVMContext();
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unsigned SysReg =
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E->getArg(0)->EvaluateKnownConstInt(getContext()).getZExtValue();
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std::string SysRegStr;
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llvm::raw_string_ostream(SysRegStr) <<
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((1 << 1) | ((SysReg >> 14) & 1)) << ":" <<
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((SysReg >> 11) & 7) << ":" <<
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((SysReg >> 7) & 15) << ":" <<
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((SysReg >> 3) & 15) << ":" <<
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( SysReg & 7);
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llvm::Metadata *Ops[] = { llvm::MDString::get(Context, SysRegStr) };
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llvm::MDNode *RegName = llvm::MDNode::get(Context, Ops);
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llvm::Value *Metadata = llvm::MetadataAsValue::get(Context, RegName);
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llvm::Type *RegisterType = Int64Ty;
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llvm::Type *ValueType = Int32Ty;
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llvm::Type *Types[] = { RegisterType };
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if (BuiltinID == AArch64::BI_ReadStatusReg) {
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llvm::Value *F = CGM.getIntrinsic(llvm::Intrinsic::read_register, Types);
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llvm::Value *Call = Builder.CreateCall(F, Metadata);
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return Builder.CreateTrunc(Call, ValueType);
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}
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llvm::Value *F = CGM.getIntrinsic(llvm::Intrinsic::write_register, Types);
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llvm::Value *ArgValue = EmitScalarExpr(E->getArg(1));
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ArgValue = Builder.CreateZExt(ArgValue, RegisterType);
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return Builder.CreateCall(F, { Metadata, ArgValue });
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}
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// Find out if any arguments are required to be integer constant
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// expressions.
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unsigned ICEArguments = 0;
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@ -870,6 +870,8 @@ __nop(void) {
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#if defined(__aarch64__)
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unsigned __int64 __getReg(int);
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long _InterlockedAdd(long volatile *Addend, long Value);
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int _ReadStatusReg(int);
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void _WriteStatusReg(int, int);
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#endif
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/*----------------------------------------------------------------------------*\
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@ -1749,6 +1749,13 @@ bool Sema::CheckAArch64BuiltinFunctionCall(unsigned BuiltinID,
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BuiltinID == AArch64::BI__builtin_arm_wsrp)
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return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, true);
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// Only check the valid encoding range. Any constant in this range would be
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// converted to a register of the form S1_2_C3_C4_5. Let the hardware throw
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// an exception for incorrect registers. This matches MSVC behavior.
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if (BuiltinID == AArch64::BI_ReadStatusReg ||
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BuiltinID == AArch64::BI_WriteStatusReg)
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return SemaBuiltinConstantArgRange(TheCall, 0, 0, 0x7fff);
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if (BuiltinID == AArch64::BI__getReg)
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return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31);
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@ -0,0 +1,117 @@
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// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm -S \
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// RUN: -o - %s | FileCheck %s -check-prefix CHECK-ASM
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// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm \
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// RUN: -o - %s | FileCheck %s -check-prefix CHECK-IR
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// From winnt.h
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#define ARM64_SYSREG(op0, op1, crn, crm, op2) \
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( ((op0 & 1) << 14) | \
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((op1 & 7) << 11) | \
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((crn & 15) << 7) | \
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((crm & 15) << 3) | \
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((op2 & 7) << 0) )
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#define ARM64_CNTVCT ARM64_SYSREG(3,3,14, 0,2) // Generic Timer counter register
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#define ARM64_PMCCNTR_EL0 ARM64_SYSREG(3,3, 9,13,0) // Cycle Count Register [CP15_PMCCNTR]
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#define ARM64_PMSELR_EL0 ARM64_SYSREG(3,3, 9,12,5) // Event Counter Selection Register [CP15_PMSELR]
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#define ARM64_PMXEVCNTR_EL0 ARM64_SYSREG(3,3, 9,13,2) // Event Count Register [CP15_PMXEVCNTR]
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#define ARM64_PMXEVCNTRn_EL0(n) ARM64_SYSREG(3,3,14, 8+((n)/8), (n)%8) // Direct Event Count Register [n/a]
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#define ARM64_TPIDR_EL0 ARM64_SYSREG(3,3,13, 0,2) // Thread ID Register, User Read/Write [CP15_TPIDRURW]
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#define ARM64_TPIDRRO_EL0 ARM64_SYSREG(3,3,13, 0,3) // Thread ID Register, User Read Only [CP15_TPIDRURO]
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#define ARM64_TPIDR_EL1 ARM64_SYSREG(3,0,13, 0,4) // Thread ID Register, Privileged Only [CP15_TPIDRPRW]
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void check_ReadWriteStatusReg(int v) {
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int ret;
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ret = _ReadStatusReg(ARM64_CNTVCT);
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// CHECK-ASM: mrs x8, CNTVCT_EL0
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// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD2:.*]])
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ret = _ReadStatusReg(ARM64_PMCCNTR_EL0);
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// CHECK-ASM: mrs x8, PMCCNTR_EL0
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// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD3:.*]])
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ret = _ReadStatusReg(ARM64_PMSELR_EL0);
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// CHECK-ASM: mrs x8, PMSELR_EL0
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// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD4:.*]])
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ret = _ReadStatusReg(ARM64_PMXEVCNTR_EL0);
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// CHECK-ASM: mrs x8, PMXEVCNTR_EL0
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// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD5:.*]])
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ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(0));
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// CHECK-ASM: mrs x8, PMEVCNTR0_EL0
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// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD6:.*]])
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ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(1));
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// CHECK-ASM: mrs x8, PMEVCNTR1_EL0
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// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD7:.*]])
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ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(30));
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// CHECK-ASM: mrs x8, PMEVCNTR30_EL0
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// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD8:.*]])
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ret = _ReadStatusReg(ARM64_TPIDR_EL0);
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// CHECK-ASM: mrs x8, TPIDR_EL0
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// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD9:.*]])
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ret = _ReadStatusReg(ARM64_TPIDRRO_EL0);
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// CHECK-ASM: mrs x8, TPIDRRO_EL0
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// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD10:.*]])
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ret = _ReadStatusReg(ARM64_TPIDR_EL1);
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// CHECK-ASM: mrs x8, TPIDR_EL1
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// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD11:.*]])
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_WriteStatusReg(ARM64_CNTVCT, v);
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// CHECK-ASM: msr S3_3_C14_C0_2, x8
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// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64 {{%.*}})
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_WriteStatusReg(ARM64_PMCCNTR_EL0, v);
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// CHECK-ASM: msr PMCCNTR_EL0, x8
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// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64 {{%.*}})
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_WriteStatusReg(ARM64_PMSELR_EL0, v);
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// CHECK-ASM: msr PMSELR_EL0, x8
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// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64 {{%.*}})
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_WriteStatusReg(ARM64_PMXEVCNTR_EL0, v);
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// CHECK-ASM: msr PMXEVCNTR_EL0, x8
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// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64 {{%.*}})
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_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(0), v);
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// CHECK-ASM: msr PMEVCNTR0_EL0, x8
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// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64 {{%.*}})
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_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(1), v);
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// CHECK-ASM: msr PMEVCNTR1_EL0, x8
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// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD7:.*]], i64 {{%.*}})
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_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(30), v);
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// CHECK-ASM: msr PMEVCNTR30_EL0, x8
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// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD8:.*]], i64 {{%.*}})
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_WriteStatusReg(ARM64_TPIDR_EL0, v);
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// CHECK-ASM: msr TPIDR_EL0, x8
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// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD9:.*]], i64 {{%.*}})
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_WriteStatusReg(ARM64_TPIDRRO_EL0, v);
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// CHECK-ASM: msr TPIDRRO_EL0, x8
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// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD10:.*]], i64 {{%.*}})
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_WriteStatusReg(ARM64_TPIDR_EL1, v);
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// CHECK-ASM: msr TPIDR_EL1, x8
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// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD11:.*]], i64 {{%.*}})
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}
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// CHECK-IR: ![[MD2]] = !{!"3:3:14:0:2"}
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// CHECK-IR: ![[MD3]] = !{!"3:3:9:13:0"}
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// CHECK-IR: ![[MD4]] = !{!"3:3:9:12:5"}
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// CHECK-IR: ![[MD5]] = !{!"3:3:9:13:2"}
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// CHECK-IR: ![[MD6]] = !{!"3:3:14:8:0"}
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// CHECK-IR: ![[MD7]] = !{!"3:3:14:8:1"}
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// CHECK-IR: ![[MD8]] = !{!"3:3:14:11:6"}
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// CHECK-IR: ![[MD9]] = !{!"3:3:13:0:2"}
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// CHECK-IR: ![[MD10]] = !{!"3:3:13:0:3"}
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// CHECK-IR: ![[MD11]] = !{!"3:0:13:0:4"}
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@ -7,3 +7,9 @@ void check__getReg() {
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__getReg(-1); // expected-error-re {{argument value {{.*}} is outside the valid range}}
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__getReg(32); // expected-error-re {{argument value {{.*}} is outside the valid range}}
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}
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void check_ReadWriteStatusReg(int v) {
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int x;
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_ReadStatusReg(x); // expected-error {{argument to '_ReadStatusReg' must be a constant integer}}
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_WriteStatusReg(x, v); // expected-error {{argument to '_WriteStatusReg' must be a constant integer}}
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}
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