diff --git a/llvm/lib/Target/TargetLowering.cpp b/llvm/lib/Target/TargetLowering.cpp
index 8951490fb6e5..5a191d999814 100644
--- a/llvm/lib/Target/TargetLowering.cpp
+++ b/llvm/lib/Target/TargetLowering.cpp
@@ -135,14 +135,14 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
 /// set operation such as a sign extend or or/xor with constant whose only
 /// use is Op.  If it returns true, the old node that sets bits which are
 /// not demanded is returned in Old, and its replacement node is returned in
-/// New, such that callers of SetBitsAreZero may call CombineTo on them if
+/// New, such that callers of DemandedBitsAreZero may call CombineTo on them if
 /// desired.
 bool TargetLowering::DemandedBitsAreZero(const SDOperand &Op, uint64_t Mask, 
                                          SDOperand &Old, SDOperand &New,
                                          SelectionDAG &DAG) {
   // If the operation has more than one use, we're not interested in it.
   // Tracking down and checking all uses would be problematic and slow.
-  if (!Op.hasOneUse())
+  if (!Op.Val->hasOneUse())
     return false;
   
   switch (Op.getOpcode()) {
@@ -164,11 +164,11 @@ bool TargetLowering::DemandedBitsAreZero(const SDOperand &Op, uint64_t Mask,
     MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
     unsigned ExtendBits = MVT::getSizeInBits(EVT);
     // If we're extending from something smaller than MVT::i64 and all of the
-    // sign extension bits are masked, return true and set New to be a zero
-    // extend inreg from the same type.
+    // sign extension bits are masked, return true and set New to be the
+    // first operand, since we no longer care what the high bits are.
     if (ExtendBits < 64 && ((Mask & (~0ULL << ExtendBits)) == 0)) {
       Old = Op;
-      New = DAG.getZeroExtendInReg(Op.getOperand(0), EVT);
+      New = Op.getOperand(0);
       return true;
     }
     break;