[ARM] Follow AACPS standard for volatile bit-fields access width
This patch resumes the work of D16586.
According to the AAPCS, volatile bit-fields should
be accessed using containers of the widht of their
declarative type. In such case:
```
struct S1 {
short a : 1;
}
```
should be accessed using load and stores of the width
(sizeof(short)), where now the compiler does only load
the minimum required width (char in this case).
However, as discussed in D16586,
that could overwrite non-volatile bit-fields, which
conflicted with C and C++ object models by creating
data race conditions that are not part of the bit-field,
e.g.
```
struct S2 {
short a;
int b : 16;
}
```
Accessing `S2.b` would also access `S2.a`.
The AAPCS Release 2020Q2
(https://documentation-service.arm.com/static/5efb7fbedbdee951c1ccf186?token=)
section 8.1 Data Types, page 36, "Volatile bit-fields -
preserving number and width of container accesses" has been
updated to avoid conflict with the C++ Memory Model.
Now it reads in the note:
```
This ABI does not place any restrictions on the access widths of bit-fields where the container
overlaps with a non-bit-field member or where the container overlaps with any zero length bit-field
placed between two other bit-fields. This is because the C/C++ memory model defines these as being
separate memory locations, which can be accessed by two threads simultaneously. For this reason,
compilers must be permitted to use a narrower memory access width (including splitting the access into
multiple instructions) to avoid writing to a different memory location. For example, in
struct S { int a:24; char b; }; a write to a must not also write to the location occupied by b, this requires at least two
memory accesses in all current Arm architectures. In the same way, in struct S { int a:24; int:0; int b:8; };,
writes to a or b must not overwrite each other.
```
I've updated the patch D16586 to follow such behavior by verifying that we
only change volatile bit-field access when:
- it won't overlap with any other non-bit-field member
- we only access memory inside the bounds of the record
- avoid overlapping zero-length bit-fields.
Regarding the number of memory accesses, that should be preserved, that will
be implemented by D67399.
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D72932
This commit is contained in:
Ties Stuij
parent
aaafe350bb
commit
208987844f
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@ -401,12 +401,15 @@ CODEGENOPT(Addrsig, 1, 0)
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/// Whether to emit unused static constants.
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CODEGENOPT(KeepStaticConsts, 1, 0)
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/// Whether to not follow the AAPCS that enforce at least one read before storing to a volatile bitfield
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/// Whether to follow the AAPCS enforcing at least one read before storing to a volatile bitfield
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CODEGENOPT(ForceAAPCSBitfieldLoad, 1, 0)
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/// Assume that by-value parameters do not alias any other values.
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CODEGENOPT(PassByValueIsNoAlias, 1, 0)
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/// Whether to not follow the AAPCS that enforces volatile bit-field access width to be
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/// according to the field declaring type width.
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CODEGENOPT(AAPCSBitfieldWidth, 1, 1)
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#undef CODEGENOPT
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#undef ENUM_CODEGENOPT
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@ -2391,9 +2391,15 @@ def mno_neg_immediates: Flag<["-"], "mno-neg-immediates">, Group<m_arm_Features_
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def mcmse : Flag<["-"], "mcmse">, Group<m_arm_Features_Group>,
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Flags<[DriverOption,CC1Option]>,
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HelpText<"Allow use of CMSE (Armv8-M Security Extensions)">;
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def ForceAAPCSBitfieldLoad : Flag<["-"], "fAAPCSBitfieldLoad">, Group<m_arm_Features_Group>,
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def ForceAAPCSBitfieldLoad : Flag<["-"], "faapcs-bitfield-load">, Group<m_arm_Features_Group>,
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Flags<[DriverOption,CC1Option]>,
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HelpText<"Follows the AAPCS standard that all volatile bit-field write generates at least one load. (ARM only).">;
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def ForceNoAAPCSBitfieldWidth : Flag<["-"], "fno-aapcs-bitfield-width">, Group<m_arm_Features_Group>,
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Flags<[DriverOption,CC1Option]>,
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HelpText<"Do not follow the AAPCS standard requirement that volatile bit-field width is dictated by the field container type. (ARM only).">;
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def AAPCSBitfieldWidth : Flag<["-"], "faapcs-bitfield-width">, Group<m_arm_Features_Group>,
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Flags<[DriverOption,CC1Option]>,
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HelpText<"Follow the AAPCS standard requirement stating that volatile bit-field width is dictated by the field container type. (ARM only).">;
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def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">, Group<m_aarch64_Features_Group>,
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HelpText<"Generate code which only uses the general purpose registers (AArch64 only)">;
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@ -1934,22 +1934,27 @@ RValue CodeGenFunction::EmitLoadOfBitfieldLValue(LValue LV,
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llvm::Type *ResLTy = ConvertType(LV.getType());
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Address Ptr = LV.getBitFieldAddress();
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llvm::Value *Val = Builder.CreateLoad(Ptr, LV.isVolatileQualified(), "bf.load");
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llvm::Value *Val =
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Builder.CreateLoad(Ptr, LV.isVolatileQualified(), "bf.load");
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bool UseVolatile = LV.isVolatileQualified() &&
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Info.VolatileStorageSize != 0 && isAAPCS(CGM.getTarget());
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const unsigned Offset = UseVolatile ? Info.VolatileOffset : Info.Offset;
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const unsigned StorageSize =
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UseVolatile ? Info.VolatileStorageSize : Info.StorageSize;
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if (Info.IsSigned) {
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assert(static_cast<unsigned>(Info.Offset + Info.Size) <= Info.StorageSize);
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unsigned HighBits = Info.StorageSize - Info.Offset - Info.Size;
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assert(static_cast<unsigned>(Offset + Info.Size) <= StorageSize);
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unsigned HighBits = StorageSize - Offset - Info.Size;
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if (HighBits)
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Val = Builder.CreateShl(Val, HighBits, "bf.shl");
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if (Info.Offset + HighBits)
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Val = Builder.CreateAShr(Val, Info.Offset + HighBits, "bf.ashr");
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if (Offset + HighBits)
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Val = Builder.CreateAShr(Val, Offset + HighBits, "bf.ashr");
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} else {
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if (Info.Offset)
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Val = Builder.CreateLShr(Val, Info.Offset, "bf.lshr");
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if (static_cast<unsigned>(Info.Offset) + Info.Size < Info.StorageSize)
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Val = Builder.CreateAnd(Val, llvm::APInt::getLowBitsSet(Info.StorageSize,
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Info.Size),
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"bf.clear");
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if (Offset)
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Val = Builder.CreateLShr(Val, Offset, "bf.lshr");
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if (static_cast<unsigned>(Offset) + Info.Size < StorageSize)
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Val = Builder.CreateAnd(
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Val, llvm::APInt::getLowBitsSet(StorageSize, Info.Size), "bf.clear");
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}
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Val = Builder.CreateIntCast(Val, ResLTy, Info.IsSigned, "bf.cast");
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EmitScalarRangeCheck(Val, LV.getType(), Loc);
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@ -2151,39 +2156,42 @@ void CodeGenFunction::EmitStoreThroughBitfieldLValue(RValue Src, LValue Dst,
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/*isSigned=*/false);
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llvm::Value *MaskedVal = SrcVal;
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const bool UseVolatile =
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CGM.getCodeGenOpts().AAPCSBitfieldWidth && Dst.isVolatileQualified() &&
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Info.VolatileStorageSize != 0 && isAAPCS(CGM.getTarget());
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const unsigned StorageSize =
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UseVolatile ? Info.VolatileStorageSize : Info.StorageSize;
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const unsigned Offset = UseVolatile ? Info.VolatileOffset : Info.Offset;
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// See if there are other bits in the bitfield's storage we'll need to load
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// and mask together with source before storing.
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if (Info.StorageSize != Info.Size) {
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assert(Info.StorageSize > Info.Size && "Invalid bitfield size.");
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if (StorageSize != Info.Size) {
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assert(StorageSize > Info.Size && "Invalid bitfield size.");
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llvm::Value *Val =
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Builder.CreateLoad(Ptr, Dst.isVolatileQualified(), "bf.load");
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Builder.CreateLoad(Ptr, Dst.isVolatileQualified(), "bf.load");
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// Mask the source value as needed.
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if (!hasBooleanRepresentation(Dst.getType()))
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SrcVal = Builder.CreateAnd(SrcVal,
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llvm::APInt::getLowBitsSet(Info.StorageSize,
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Info.Size),
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"bf.value");
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SrcVal = Builder.CreateAnd(
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SrcVal, llvm::APInt::getLowBitsSet(StorageSize, Info.Size),
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"bf.value");
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MaskedVal = SrcVal;
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if (Info.Offset)
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SrcVal = Builder.CreateShl(SrcVal, Info.Offset, "bf.shl");
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if (Offset)
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SrcVal = Builder.CreateShl(SrcVal, Offset, "bf.shl");
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// Mask out the original value.
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Val = Builder.CreateAnd(Val,
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~llvm::APInt::getBitsSet(Info.StorageSize,
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Info.Offset,
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Info.Offset + Info.Size),
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"bf.clear");
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Val = Builder.CreateAnd(
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Val, ~llvm::APInt::getBitsSet(StorageSize, Offset, Offset + Info.Size),
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"bf.clear");
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// Or together the unchanged values and the source value.
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SrcVal = Builder.CreateOr(Val, SrcVal, "bf.set");
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} else {
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assert(Info.Offset == 0);
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assert(Offset == 0);
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// According to the AACPS:
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// When a volatile bit-field is written, and its container does not overlap
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// with any non-bit-field member, its container must be read exactly once and
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// written exactly once using the access width appropriate to the type of the
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// container. The two accesses are not atomic.
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// with any non-bit-field member, its container must be read exactly once
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// and written exactly once using the access width appropriate to the type
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// of the container. The two accesses are not atomic.
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if (Dst.isVolatileQualified() && isAAPCS(CGM.getTarget()) &&
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CGM.getCodeGenOpts().ForceAAPCSBitfieldLoad)
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Builder.CreateLoad(Ptr, true, "bf.load");
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@ -2198,8 +2206,8 @@ void CodeGenFunction::EmitStoreThroughBitfieldLValue(RValue Src, LValue Dst,
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// Sign extend the value if needed.
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if (Info.IsSigned) {
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assert(Info.Size <= Info.StorageSize);
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unsigned HighBits = Info.StorageSize - Info.Size;
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assert(Info.Size <= StorageSize);
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unsigned HighBits = StorageSize - Info.Size;
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if (HighBits) {
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ResultVal = Builder.CreateShl(ResultVal, HighBits, "bf.result.shl");
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ResultVal = Builder.CreateAShr(ResultVal, HighBits, "bf.result.ashr");
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@ -4211,32 +4219,45 @@ LValue CodeGenFunction::EmitLValueForField(LValue base,
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if (field->isBitField()) {
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const CGRecordLayout &RL =
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CGM.getTypes().getCGRecordLayout(field->getParent());
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CGM.getTypes().getCGRecordLayout(field->getParent());
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const CGBitFieldInfo &Info = RL.getBitFieldInfo(field);
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const bool UseVolatile = isAAPCS(CGM.getTarget()) &&
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CGM.getCodeGenOpts().AAPCSBitfieldWidth &&
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Info.VolatileStorageSize != 0 &&
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field->getType()
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.withCVRQualifiers(base.getVRQualifiers())
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.isVolatileQualified();
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Address Addr = base.getAddress(*this);
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unsigned Idx = RL.getLLVMFieldNo(field);
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const RecordDecl *rec = field->getParent();
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if (!IsInPreservedAIRegion &&
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(!getDebugInfo() || !rec->hasAttr<BPFPreserveAccessIndexAttr>())) {
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if (Idx != 0)
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// For structs, we GEP to the field that the record layout suggests.
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Addr = Builder.CreateStructGEP(Addr, Idx, field->getName());
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} else {
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llvm::DIType *DbgInfo = getDebugInfo()->getOrCreateRecordType(
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getContext().getRecordType(rec), rec->getLocation());
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Addr = Builder.CreatePreserveStructAccessIndex(Addr, Idx,
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getDebugInfoFIndex(rec, field->getFieldIndex()),
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DbgInfo);
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if (!UseVolatile) {
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if (!IsInPreservedAIRegion &&
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(!getDebugInfo() || !rec->hasAttr<BPFPreserveAccessIndexAttr>())) {
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if (Idx != 0)
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// For structs, we GEP to the field that the record layout suggests.
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Addr = Builder.CreateStructGEP(Addr, Idx, field->getName());
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} else {
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llvm::DIType *DbgInfo = getDebugInfo()->getOrCreateRecordType(
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getContext().getRecordType(rec), rec->getLocation());
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Addr = Builder.CreatePreserveStructAccessIndex(
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Addr, Idx, getDebugInfoFIndex(rec, field->getFieldIndex()),
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DbgInfo);
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}
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}
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const unsigned SS =
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UseVolatile ? Info.VolatileStorageSize : Info.StorageSize;
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// Get the access type.
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llvm::Type *FieldIntTy =
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llvm::Type::getIntNTy(getLLVMContext(), Info.StorageSize);
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llvm::Type *FieldIntTy = llvm::Type::getIntNTy(getLLVMContext(), SS);
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if (Addr.getElementType() != FieldIntTy)
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Addr = Builder.CreateElementBitCast(Addr, FieldIntTy);
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if (UseVolatile) {
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const unsigned VolatileOffset = Info.VolatileStorageOffset.getQuantity();
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if (VolatileOffset)
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Addr = Builder.CreateConstInBoundsGEP(Addr, VolatileOffset);
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}
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QualType fieldType =
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field->getType().withCVRQualifiers(base.getVRQualifiers());
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field->getType().withCVRQualifiers(base.getVRQualifiers());
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// TODO: Support TBAA for bit fields.
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LValueBaseInfo FieldBaseInfo(BaseInfo.getAlignmentSource());
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return LValue::MakeBitfield(Addr, Info, fieldType, FieldBaseInfo,
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@ -46,7 +46,7 @@ namespace CodeGen {
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/// };
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///
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/// This will end up as the following LLVM type. The first array is the
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/// bitfield, and the second is the padding out to a 4-byte alignmnet.
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/// bitfield, and the second is the padding out to a 4-byte alignment.
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///
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/// %t = type { i8, i8, i8, i8, i8, [3 x i8] }
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///
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@ -80,8 +80,21 @@ struct CGBitFieldInfo {
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/// The offset of the bitfield storage from the start of the struct.
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CharUnits StorageOffset;
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/// The offset within a contiguous run of bitfields that are represented as a
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/// single "field" within the LLVM struct type, taking into account the AAPCS
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/// rules for volatile bitfields. This offset is in bits.
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unsigned VolatileOffset : 16;
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/// The storage size in bits which should be used when accessing this
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/// bitfield.
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unsigned VolatileStorageSize;
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/// The offset of the bitfield storage from the start of the struct.
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CharUnits VolatileStorageOffset;
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CGBitFieldInfo()
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: Offset(), Size(), IsSigned(), StorageSize(), StorageOffset() {}
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: Offset(), Size(), IsSigned(), StorageSize(), StorageOffset(),
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VolatileOffset(), VolatileStorageSize(), VolatileStorageOffset() {}
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CGBitFieldInfo(unsigned Offset, unsigned Size, bool IsSigned,
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unsigned StorageSize, CharUnits StorageOffset)
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@ -109,6 +109,14 @@ struct CGRecordLowering {
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D->isMsStruct(Context);
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}
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/// Helper function to check if we are targeting AAPCS.
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bool isAAPCS() const {
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return Context.getTargetInfo().getABI().startswith("aapcs");
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}
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/// Helper function to check if the target machine is BigEndian.
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bool isBE() const { return Context.getTargetInfo().isBigEndian(); }
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/// The Itanium base layout rule allows virtual bases to overlap
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/// other bases, which complicates layout in specific ways.
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///
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@ -172,7 +180,8 @@ struct CGRecordLowering {
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void lowerUnion();
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void accumulateFields();
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void accumulateBitFields(RecordDecl::field_iterator Field,
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RecordDecl::field_iterator FieldEnd);
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RecordDecl::field_iterator FieldEnd);
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void computeVolatileBitfields();
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void accumulateBases();
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void accumulateVPtrs();
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void accumulateVBases();
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@ -237,6 +246,10 @@ void CGRecordLowering::setBitFieldInfo(
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// least-significant-bit.
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if (DataLayout.isBigEndian())
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Info.Offset = Info.StorageSize - (Info.Offset + Info.Size);
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Info.VolatileStorageSize = 0;
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Info.VolatileOffset = 0;
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Info.VolatileStorageOffset = CharUnits::Zero();
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}
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void CGRecordLowering::lower(bool NVBaseType) {
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@ -261,15 +274,21 @@ void CGRecordLowering::lower(bool NVBaseType) {
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// 8) Format the complete list of members in a way that can be consumed by
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// CodeGenTypes::ComputeRecordLayout.
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CharUnits Size = NVBaseType ? Layout.getNonVirtualSize() : Layout.getSize();
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if (D->isUnion())
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return lowerUnion();
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if (D->isUnion()) {
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lowerUnion();
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computeVolatileBitfields();
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return;
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}
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accumulateFields();
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// RD implies C++.
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if (RD) {
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accumulateVPtrs();
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accumulateBases();
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if (Members.empty())
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return appendPaddingBytes(Size);
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if (Members.empty()) {
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appendPaddingBytes(Size);
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computeVolatileBitfields();
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return;
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}
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if (!NVBaseType)
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accumulateVBases();
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}
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@ -281,6 +300,7 @@ void CGRecordLowering::lower(bool NVBaseType) {
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Members.pop_back();
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calculateZeroInit();
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fillOutputFields();
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computeVolatileBitfields();
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}
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void CGRecordLowering::lowerUnion() {
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@ -418,9 +438,9 @@ CGRecordLowering::accumulateBitFields(RecordDecl::field_iterator Field,
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if (OffsetInRecord < 8 || !llvm::isPowerOf2_64(OffsetInRecord) ||
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!DataLayout.fitsInLegalInteger(OffsetInRecord))
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return false;
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// Make sure StartBitOffset is natually aligned if it is treated as an
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// Make sure StartBitOffset is naturally aligned if it is treated as an
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// IType integer.
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if (StartBitOffset %
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if (StartBitOffset %
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Context.toBits(getAlignment(getIntNType(OffsetInRecord))) !=
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0)
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return false;
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@ -503,6 +523,123 @@ void CGRecordLowering::accumulateBases() {
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}
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}
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/// The AAPCS that defines that, when possible, bit-fields should
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/// be accessed using containers of the declared type width:
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/// When a volatile bit-field is read, and its container does not overlap with
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/// any non-bit-field member or any zero length bit-field member, its container
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/// must be read exactly once using the access width appropriate to the type of
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/// the container. When a volatile bit-field is written, and its container does
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/// not overlap with any non-bit-field member or any zero-length bit-field
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/// member, its container must be read exactly once and written exactly once
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/// using the access width appropriate to the type of the container. The two
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/// accesses are not atomic.
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///
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/// Enforcing the width restriction can be disabled using
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/// -fno-aapcs-bitfield-width.
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void CGRecordLowering::computeVolatileBitfields() {
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if (!isAAPCS() || !Types.getCodeGenOpts().AAPCSBitfieldWidth)
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return;
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for (auto &I : BitFields) {
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const FieldDecl *Field = I.first;
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CGBitFieldInfo &Info = I.second;
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llvm::Type *ResLTy = Types.ConvertTypeForMem(Field->getType());
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// If the record alignment is less than the type width, we can't enforce a
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// aligned load, bail out.
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if ((uint64_t)(Context.toBits(Layout.getAlignment())) <
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ResLTy->getPrimitiveSizeInBits())
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continue;
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// CGRecordLowering::setBitFieldInfo() pre-adjusts the bit-field offsets
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// for big-endian targets, but it assumes a container of width
|
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// Info.StorageSize. Since AAPCS uses a different container size (width
|
||||
// of the type), we first undo that calculation here and redo it once
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// the bit-field offset within the new container is calculated.
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const unsigned OldOffset =
|
||||
isBE() ? Info.StorageSize - (Info.Offset + Info.Size) : Info.Offset;
|
||||
// Offset to the bit-field from the beginning of the struct.
|
||||
const unsigned AbsoluteOffset =
|
||||
Context.toBits(Info.StorageOffset) + OldOffset;
|
||||
|
||||
// Container size is the width of the bit-field type.
|
||||
const unsigned StorageSize = ResLTy->getPrimitiveSizeInBits();
|
||||
// Nothing to do if the access uses the desired
|
||||
// container width and is naturally aligned.
|
||||
if (Info.StorageSize == StorageSize && (OldOffset % StorageSize == 0))
|
||||
continue;
|
||||
|
||||
// Offset within the container.
|
||||
unsigned Offset = AbsoluteOffset & (StorageSize - 1);
|
||||
// Bail out if an aligned load of the container cannot cover the entire
|
||||
// bit-field. This can happen for example, if the bit-field is part of a
|
||||
// packed struct. AAPCS does not define access rules for such cases, we let
|
||||
// clang to follow its own rules.
|
||||
if (Offset + Info.Size > StorageSize)
|
||||
continue;
|
||||
|
||||
// Re-adjust offsets for big-endian targets.
|
||||
if (isBE())
|
||||
Offset = StorageSize - (Offset + Info.Size);
|
||||
|
||||
const CharUnits StorageOffset =
|
||||
Context.toCharUnitsFromBits(AbsoluteOffset & ~(StorageSize - 1));
|
||||
const CharUnits End = StorageOffset +
|
||||
Context.toCharUnitsFromBits(StorageSize) -
|
||||
CharUnits::One();
|
||||
|
||||
const ASTRecordLayout &Layout =
|
||||
Context.getASTRecordLayout(Field->getParent());
|
||||
// If we access outside memory outside the record, than bail out.
|
||||
const CharUnits RecordSize = Layout.getSize();
|
||||
if (End >= RecordSize)
|
||||
continue;
|
||||
|
||||
// Bail out if performing this load would access non-bit-fields members.
|
||||
bool Conflict = false;
|
||||
for (const auto *F : D->fields()) {
|
||||
// Allow sized bit-fields overlaps.
|
||||
if (F->isBitField() && !F->isZeroLengthBitField(Context))
|
||||
continue;
|
||||
|
||||
const CharUnits FOffset = Context.toCharUnitsFromBits(
|
||||
Layout.getFieldOffset(F->getFieldIndex()));
|
||||
|
||||
// As C11 defines, a zero sized bit-field defines a barrier, so
|
||||
// fields after and before it should be race condition free.
|
||||
// The AAPCS acknowledges it and imposes no restritions when the
|
||||
// natural container overlaps a zero-length bit-field.
|
||||
if (F->isZeroLengthBitField(Context)) {
|
||||
if (End > FOffset && StorageOffset < FOffset) {
|
||||
Conflict = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
const CharUnits FEnd =
|
||||
FOffset +
|
||||
Context.toCharUnitsFromBits(
|
||||
Types.ConvertTypeForMem(F->getType())->getPrimitiveSizeInBits()) -
|
||||
CharUnits::One();
|
||||
// If no overlap, continue.
|
||||
if (End < FOffset || FEnd < StorageOffset)
|
||||
continue;
|
||||
|
||||
// The desired load overlaps a non-bit-field member, bail out.
|
||||
Conflict = true;
|
||||
break;
|
||||
}
|
||||
|
||||
if (Conflict)
|
||||
continue;
|
||||
// Write the new bit-field access parameters.
|
||||
// As the storage offset now is defined as the number of elements from the
|
||||
// start of the structure, we should divide the Offset by the element size.
|
||||
Info.VolatileStorageOffset =
|
||||
StorageOffset / Context.toCharUnitsFromBits(StorageSize).getQuantity();
|
||||
Info.VolatileStorageSize = StorageSize;
|
||||
Info.VolatileOffset = Offset;
|
||||
}
|
||||
}
|
||||
|
||||
void CGRecordLowering::accumulateVPtrs() {
|
||||
if (Layout.hasOwnVFPtr())
|
||||
Members.push_back(MemberInfo(CharUnits::Zero(), MemberInfo::VFPtr,
|
||||
|
|
@ -848,8 +985,10 @@ CodeGenTypes::ComputeRecordLayout(const RecordDecl *D, llvm::StructType *Ty) {
|
|||
assert(Info.StorageSize <= SL->getSizeInBits() &&
|
||||
"Union not large enough for bitfield storage");
|
||||
} else {
|
||||
assert(Info.StorageSize ==
|
||||
getDataLayout().getTypeAllocSizeInBits(ElementTy) &&
|
||||
assert((Info.StorageSize ==
|
||||
getDataLayout().getTypeAllocSizeInBits(ElementTy) ||
|
||||
Info.VolatileStorageSize ==
|
||||
getDataLayout().getTypeAllocSizeInBits(ElementTy)) &&
|
||||
"Storage size does not match the element type size");
|
||||
}
|
||||
assert(Info.Size > 0 && "Empty bitfield!");
|
||||
|
|
@ -897,11 +1036,12 @@ LLVM_DUMP_METHOD void CGRecordLayout::dump() const {
|
|||
|
||||
void CGBitFieldInfo::print(raw_ostream &OS) const {
|
||||
OS << "<CGBitFieldInfo"
|
||||
<< " Offset:" << Offset
|
||||
<< " Size:" << Size
|
||||
<< " IsSigned:" << IsSigned
|
||||
<< " Offset:" << Offset << " Size:" << Size << " IsSigned:" << IsSigned
|
||||
<< " StorageSize:" << StorageSize
|
||||
<< " StorageOffset:" << StorageOffset.getQuantity() << ">";
|
||||
<< " StorageOffset:" << StorageOffset.getQuantity()
|
||||
<< " VolatileOffset:" << VolatileOffset
|
||||
<< " VolatileStorageSize:" << VolatileStorageSize
|
||||
<< " VolatileStorageOffset:" << VolatileStorageOffset.getQuantity() << ">";
|
||||
}
|
||||
|
||||
LLVM_DUMP_METHOD void CGBitFieldInfo::dump() const {
|
||||
|
|
|
|||
|
|
@ -1464,8 +1464,11 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
|
|||
std::string(Args.getLastArgValue(OPT_fsymbol_partition_EQ));
|
||||
|
||||
Opts.ForceAAPCSBitfieldLoad = Args.hasArg(OPT_ForceAAPCSBitfieldLoad);
|
||||
Opts.AAPCSBitfieldWidth =
|
||||
Args.hasFlag(OPT_AAPCSBitfieldWidth, OPT_ForceNoAAPCSBitfieldWidth, true);
|
||||
|
||||
Opts.PassByValueIsNoAlias = Args.hasArg(OPT_fpass_by_value_is_noalias);
|
||||
|
||||
return Success;
|
||||
}
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -14,7 +14,7 @@
|
|||
// CHECK-RECORD: LLVMType:%struct.s0 = type { [3 x i8] }
|
||||
// CHECK-RECORD: IsZeroInitializable:1
|
||||
// CHECK-RECORD: BitFields:[
|
||||
// CHECK-RECORD: <CGBitFieldInfo Offset:0 Size:24 IsSigned:1 StorageSize:24 StorageOffset:0>
|
||||
// CHECK-RECORD: <CGBitFieldInfo Offset:0 Size:24 IsSigned:1 StorageSize:24 StorageOffset:0
|
||||
struct __attribute((packed)) s0 {
|
||||
int f0 : 24;
|
||||
};
|
||||
|
|
@ -54,8 +54,8 @@ unsigned long long test_0() {
|
|||
// CHECK-RECORD: LLVMType:%struct.s1 = type { [3 x i8] }
|
||||
// CHECK-RECORD: IsZeroInitializable:1
|
||||
// CHECK-RECORD: BitFields:[
|
||||
// CHECK-RECORD: <CGBitFieldInfo Offset:0 Size:10 IsSigned:1 StorageSize:24 StorageOffset:0>
|
||||
// CHECK-RECORD: <CGBitFieldInfo Offset:10 Size:10 IsSigned:1 StorageSize:24 StorageOffset:0>
|
||||
// CHECK-RECORD: <CGBitFieldInfo Offset:0 Size:10 IsSigned:1 StorageSize:24 StorageOffset:0
|
||||
// CHECK-RECORD: <CGBitFieldInfo Offset:10 Size:10 IsSigned:1 StorageSize:24 StorageOffset:0
|
||||
|
||||
#pragma pack(push)
|
||||
#pragma pack(1)
|
||||
|
|
@ -102,7 +102,7 @@ unsigned long long test_1() {
|
|||
// CHECK-RECORD: LLVMType:%union.u2 = type { i8 }
|
||||
// CHECK-RECORD: IsZeroInitializable:1
|
||||
// CHECK-RECORD: BitFields:[
|
||||
// CHECK-RECORD: <CGBitFieldInfo Offset:0 Size:3 IsSigned:0 StorageSize:8 StorageOffset:0>
|
||||
// CHECK-RECORD: <CGBitFieldInfo Offset:0 Size:3 IsSigned:0 StorageSize:8 StorageOffset:0
|
||||
|
||||
union __attribute__((packed)) u2 {
|
||||
unsigned long long f0 : 3;
|
||||
|
|
@ -274,8 +274,8 @@ _Bool test_6() {
|
|||
// CHECK-RECORD: LLVMType:%struct.s7 = type { i32, i32, i32, i8, i32, [12 x i8] }
|
||||
// CHECK-RECORD: IsZeroInitializable:1
|
||||
// CHECK-RECORD: BitFields:[
|
||||
// CHECK-RECORD: <CGBitFieldInfo Offset:0 Size:5 IsSigned:1 StorageSize:8 StorageOffset:12>
|
||||
// CHECK-RECORD: <CGBitFieldInfo Offset:0 Size:29 IsSigned:1 StorageSize:32 StorageOffset:16>
|
||||
// CHECK-RECORD: <CGBitFieldInfo Offset:0 Size:5 IsSigned:1 StorageSize:8 StorageOffset:12
|
||||
// CHECK-RECORD: <CGBitFieldInfo Offset:0 Size:29 IsSigned:1 StorageSize:32 StorageOffset:16
|
||||
|
||||
struct __attribute__((aligned(16))) s7 {
|
||||
int a, b, c;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
// RUN: %clang_cc1 -triple=%itanium_abi_triple -emit-llvm < %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-IT
|
||||
// RUN: %clang_cc1 -triple=aarch64-unknown-linux-gnu -emit-llvm < %s | FileCheck %s -check-prefix CHECK -check-prefixes CHECK-IT,CHECK-IT-ARM
|
||||
// RUN: %clang_cc1 -triple=x86_64-unknown-linux-gnu -emit-llvm < %s | FileCheck %s -check-prefix CHECK -check-prefixes CHECK-IT,CHECK-IT-OTHER
|
||||
// RUN: %clang_cc1 -triple=%ms_abi_triple -emit-llvm < %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-MS
|
||||
|
||||
int S;
|
||||
|
|
@ -88,7 +89,8 @@ int main() {
|
|||
// CHECK-MS: load i32, i32* getelementptr {{.*}} @BF
|
||||
// CHECK: store i32 {{.*}}, i32* [[I]]
|
||||
i=vBF.x;
|
||||
// CHECK-IT: load volatile i8, i8* getelementptr {{.*}} @vBF
|
||||
// CHECK-IT-OTHER: load volatile i8, i8* getelementptr {{.*}} @vBF
|
||||
// CHECK-IT-ARM: load volatile i32, i32* bitcast {{.*}} @vBF
|
||||
// CHECK-MS: load volatile i32, i32* getelementptr {{.*}} @vBF
|
||||
// CHECK: store i32 {{.*}}, i32* [[I]]
|
||||
i=V[3];
|
||||
|
|
@ -163,9 +165,11 @@ int main() {
|
|||
// CHECK-MS: store i32 {{.*}}, i32* getelementptr {{.*}} @BF
|
||||
vBF.x=i;
|
||||
// CHECK: load i32, i32* [[I]]
|
||||
// CHECK-IT: load volatile i8, i8* getelementptr {{.*}} @vBF
|
||||
// CHECK-IT-OTHER: load volatile i8, i8* getelementptr {{.*}} @vBF
|
||||
// CHECK-IT-ARM: load volatile i32, i32* bitcast {{.*}} @vBF
|
||||
// CHECK-MS: load volatile i32, i32* getelementptr {{.*}} @vBF
|
||||
// CHECK-IT: store volatile i8 {{.*}}, i8* getelementptr {{.*}} @vBF
|
||||
// CHECK-IT-OTHER: store volatile i8 {{.*}}, i8* getelementptr {{.*}} @vBF
|
||||
// CHECK-IT-ARM: store volatile i32 {{.*}}, i32* bitcast {{.*}} @vBF
|
||||
// CHECK-MS: store volatile i32 {{.*}}, i32* getelementptr {{.*}} @vBF
|
||||
V[3]=i;
|
||||
// CHECK: load i32, i32* [[I]]
|
||||
|
|
|
|||
Loading…
Reference in New Issue