parent
3064f9aaa6
commit
20712deecb
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@ -852,7 +852,7 @@ def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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[(set VR128:$dst, (v4f32 (vector_shuffle
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VR128:$src, (undef),
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MOVSHDUP_shuffle_mask)))]>;
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def MOVSHDUPrm : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
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def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"movshdup {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (v4f32 (vector_shuffle
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(loadv4f32 addr:$src), (undef),
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@ -863,7 +863,7 @@ def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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[(set VR128:$dst, (v4f32 (vector_shuffle
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VR128:$src, (undef),
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MOVSLDUP_shuffle_mask)))]>;
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def MOVSLDUPrm : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
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def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"movsldup {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (v4f32 (vector_shuffle
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(loadv4f32 addr:$src), (undef),
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@ -874,10 +874,11 @@ def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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[(set VR128:$dst, (v2f64 (vector_shuffle
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VR128:$src, (undef),
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SSE_splat_v2_mask)))]>;
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def MOVDDUPrm : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
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def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
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"movddup {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (v2f64 (vector_shuffle
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(loadv2f64 addr:$src), (undef),
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(scalar_to_vector (loadf64 addr:$src)),
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(undef),
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SSE_splat_v2_mask)))]>;
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// SSE2 instructions without OpSize prefix
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