Add support for parsing the writeback ("!") token.
llvm-svn: 119761
This commit is contained in:
Bill Wendling
parent
5a97bd873e
commit
2063b84297
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@ -50,10 +50,10 @@ class ARMAsmParser : public TargetAsmParser {
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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int TryParseRegister();
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ARMOperand *TryParseRegisterWithWriteBack();
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ARMOperand *ParseRegisterList();
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ARMOperand *ParseMemory();
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ARMOperand *ParseOperand();
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bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &);
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bool ParseMemoryOffsetReg(bool &Negative,
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bool &OffsetRegShifted,
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@ -127,7 +127,6 @@ class ARMOperand : public MCParsedAsmOperand {
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struct {
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unsigned RegNum;
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bool Writeback;
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} Reg;
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struct {
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@ -142,11 +141,11 @@ class ARMOperand : public MCParsedAsmOperand {
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const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
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enum ShiftType ShiftType; // used when OffsetRegShifted is true
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unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
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unsigned Preindexed : 1;
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unsigned Postindexed : 1;
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unsigned OffsetIsReg : 1;
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unsigned Negative : 1; // only used when OffsetIsReg is true
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unsigned Writeback : 1;
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unsigned Preindexed : 1;
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unsigned Postindexed : 1;
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unsigned OffsetIsReg : 1;
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unsigned Negative : 1; // only used when OffsetIsReg is true
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unsigned Writeback : 1;
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} Mem;
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};
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@ -322,11 +321,9 @@ public:
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return Op;
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}
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static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
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SMLoc E) {
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static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
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ARMOperand *Op = new ARMOperand(Register);
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Op->Reg.RegNum = RegNum;
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Op->Reg.Writeback = Writeback;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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@ -396,10 +393,10 @@ void ARMOperand::dump(raw_ostream &OS) const {
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getImm()->print(OS);
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break;
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case Memory:
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OS << "<memory" << (!Mem.Writeback ? ">" : "!>");
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OS << "<memory>";
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break;
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case Register:
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OS << "<register " << getReg() << (!Reg.Writeback ? ">" : "!>");
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OS << "<register " << getReg() << ">";
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break;
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case RegisterList:
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case DPRRegisterList:
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@ -447,34 +444,35 @@ int ARMAsmParser::TryParseRegister() {
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}
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/// Try to parse a register name. The token must be an Identifier when called,
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/// and if it is a register name the token is eaten and the register number is
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/// returned. Otherwise return -1.
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/// Try to parse a register name. The token must be an Identifier when called.
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/// If it's a register, an AsmOperand is created. Another AsmOperand is created
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/// if there is a "writeback". 'true' if it's not a register.
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///
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/// TODO this is likely to change to allow different register types and or to
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/// parse for a specific register type.
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ARMOperand *ARMAsmParser::TryParseRegisterWithWriteBack() {
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bool ARMAsmParser::
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TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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int RegNo = TryParseRegister();
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if (RegNo == -1)
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return 0;
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return true;
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SMLoc E = Parser.getTok().getLoc();
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Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
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bool Writeback = false;
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const AsmToken &ExclaimTok = Parser.getTok();
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if (ExclaimTok.is(AsmToken::Exclaim)) {
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E = ExclaimTok.getLoc();
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Writeback = true;
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Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
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ExclaimTok.getLoc()));
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Parser.Lex(); // Eat exclaim token
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}
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return ARMOperand::CreateReg(RegNo, Writeback, S, E);
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return false;
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}
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/// Parse a register list, return it if successful else return null. The first
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/// token must be a '{' when called.
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ARMOperand *ARMAsmParser::ParseRegisterList() {
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bool ARMAsmParser::
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ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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assert(Parser.getTok().is(AsmToken::LCurly) &&
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"Token is not a Left Curly Brace");
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SMLoc S = Parser.getTok().getLoc();
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@ -491,13 +489,13 @@ ARMOperand *ARMAsmParser::ParseRegisterList() {
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SMLoc RegLoc = RegTok.getLoc();
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if (RegTok.isNot(AsmToken::Identifier)) {
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Error(RegLoc, "register expected");
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return 0;
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return true;
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}
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int RegNum = TryParseRegister();
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if (RegNum == -1) {
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Error(RegLoc, "register expected");
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return 0;
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return true;
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}
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if (IsRange) {
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@ -518,7 +516,7 @@ ARMOperand *ARMAsmParser::ParseRegisterList() {
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const AsmToken &RCurlyTok = Parser.getTok();
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if (RCurlyTok.isNot(AsmToken::RCurly)) {
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Error(RCurlyTok.getLoc(), "'}' expected");
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return 0;
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return true;
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}
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SMLoc E = RCurlyTok.getLoc();
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@ -540,7 +538,7 @@ ARMOperand *ARMAsmParser::ParseRegisterList() {
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if (RegMap[Reg]) {
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Error(RegInfo.second, "register duplicated in register list");
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return 0;
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return true;
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}
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if (!EmittedWarning && Reg < HighRegNum)
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@ -551,14 +549,17 @@ ARMOperand *ARMAsmParser::ParseRegisterList() {
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HighRegNum = std::max(Reg, HighRegNum);
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}
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return ARMOperand::CreateRegList(Registers, S, E);
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Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
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return false;
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}
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/// Parse an ARM memory expression, return false if successful else return true
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/// or an error. The first token must be a '[' when called.
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///
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/// TODO Only preindexing and postindexing addressing are started, unindexed
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/// with option, etc are still to do.
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ARMOperand *ARMAsmParser::ParseMemory() {
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bool ARMAsmParser::
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ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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SMLoc S, E;
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assert(Parser.getTok().is(AsmToken::LBrac) &&
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"Token is not a Left Bracket");
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@ -568,12 +569,12 @@ ARMOperand *ARMAsmParser::ParseMemory() {
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const AsmToken &BaseRegTok = Parser.getTok();
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if (BaseRegTok.isNot(AsmToken::Identifier)) {
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Error(BaseRegTok.getLoc(), "register expected");
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return 0;
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return true;
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}
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int BaseRegNum = TryParseRegister();
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if (BaseRegNum == -1) {
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Error(BaseRegTok.getLoc(), "register expected");
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return 0;
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return true;
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}
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bool Preindexed = false;
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@ -595,25 +596,34 @@ ARMOperand *ARMAsmParser::ParseMemory() {
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const MCExpr *Offset;
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if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
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Offset, OffsetIsReg, OffsetRegNum, E))
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return 0;
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return true;
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const AsmToken &RBracTok = Parser.getTok();
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if (RBracTok.isNot(AsmToken::RBrac)) {
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Error(RBracTok.getLoc(), "']' expected");
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return 0;
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return true;
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}
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E = RBracTok.getLoc();
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Parser.Lex(); // Eat right bracket token.
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const AsmToken &ExclaimTok = Parser.getTok();
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ARMOperand *WBOp = 0;
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if (ExclaimTok.is(AsmToken::Exclaim)) {
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E = ExclaimTok.getLoc();
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WBOp = ARMOperand::CreateToken(ExclaimTok.getString(),
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ExclaimTok.getLoc());
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Writeback = true;
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Parser.Lex(); // Eat exclaim token
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}
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return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
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OffsetRegShifted, ShiftType, ShiftAmount,
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Preindexed, Postindexed, Negative, Writeback,
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S, E);
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Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
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OffsetRegNum, OffsetRegShifted,
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ShiftType, ShiftAmount, Preindexed,
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Postindexed, Negative, Writeback,
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S, E));
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if (WBOp)
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Operands.push_back(WBOp);
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return false;
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}
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// The "[Rn" we have so far was not followed by a comma.
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else if (Tok.is(AsmToken::RBrac)) {
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@ -629,27 +639,33 @@ ARMOperand *ARMAsmParser::ParseMemory() {
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const MCExpr *Offset = 0;
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const AsmToken &NextTok = Parser.getTok();
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if (NextTok.isNot(AsmToken::EndOfStatement)) {
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Postindexed = true;
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Writeback = true;
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if (NextTok.isNot(AsmToken::Comma)) {
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Error(NextTok.getLoc(), "',' expected");
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return 0;
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return true;
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}
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Parser.Lex(); // Eat comma token.
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if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
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ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
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E))
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return 0;
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return true;
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}
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return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
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OffsetRegShifted, ShiftType, ShiftAmount,
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Preindexed, Postindexed, Negative, Writeback,
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S, E);
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Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
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OffsetRegNum, OffsetRegShifted,
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ShiftType, ShiftAmount, Preindexed,
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Postindexed, Negative, Writeback,
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S, E));
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return false;
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}
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return 0;
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return true;
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}
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/// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
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@ -760,28 +776,30 @@ bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
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/// Parse a arm instruction operand. For now this parses the operand regardless
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/// of the mnemonic.
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ARMOperand *ARMAsmParser::ParseOperand() {
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bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands){
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SMLoc S, E;
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switch (getLexer().getKind()) {
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default:
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Error(Parser.getTok().getLoc(), "unexpected token in operand");
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return 0;
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case AsmToken::Identifier:
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if (ARMOperand *Op = TryParseRegisterWithWriteBack())
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return Op;
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return true;
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case AsmToken::Identifier: {
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if (!TryParseRegisterWithWriteBack(Operands))
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return false;
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// This was not a register so parse other operands that start with an
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// identifier (like labels) as expressions and create them as immediates.
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const MCExpr *IdVal;
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S = Parser.getTok().getLoc();
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if (getParser().ParseExpression(IdVal))
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return 0;
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return true;
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E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
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return ARMOperand::CreateImm(IdVal, S, E);
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Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
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return false;
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}
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case AsmToken::LBrac:
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return ParseMemory();
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return ParseMemory(Operands);
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case AsmToken::LCurly:
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return ParseRegisterList();
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return ParseRegisterList(Operands);
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case AsmToken::Hash:
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// #42 -> immediate.
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// TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
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@ -789,9 +807,10 @@ ARMOperand *ARMAsmParser::ParseOperand() {
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Parser.Lex();
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const MCExpr *ImmVal;
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if (getParser().ParseExpression(ImmVal))
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return 0;
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return true;
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E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
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return ARMOperand::CreateImm(ImmVal, S, E);
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Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
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return false;
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}
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}
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@ -853,9 +872,7 @@ bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
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// Read the remaining operands.
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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// Read the first operand.
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if (ARMOperand *Op = ParseOperand())
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Operands.push_back(Op);
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else {
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if (ParseOperand(Operands)) {
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Parser.EatToEndOfStatement();
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return true;
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}
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@ -864,9 +881,7 @@ bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
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Parser.Lex(); // Eat the comma.
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// Parse and remember the operand.
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if (ARMOperand *Op = ParseOperand())
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Operands.push_back(Op);
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else {
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if (ParseOperand(Operands)) {
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Parser.EatToEndOfStatement();
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return true;
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}
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@ -33,3 +33,21 @@
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stmib r2, {r1,r3-r6,sp}
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stmda r2, {r1,r3-r6,sp}
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stmdb r2, {r1,r3-r6,sp}
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@ CHECK: ldmia r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe8]
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@ CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe9]
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@ CHECK: ldmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe8]
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@ CHECK: ldmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe9]
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ldmia r2!, {r1,r3-r6,sp}
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ldmib r2!, {r1,r3-r6,sp}
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ldmda r2!, {r1,r3-r6,sp}
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ldmdb r2!, {r1,r3-r6,sp}
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@ CHECK: stmia r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe8]
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@ CHECK: stmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe9]
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@ CHECK: stmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe8]
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@ CHECK: stmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe9]
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stmia r2!, {r1,r3-r6,sp}
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stmib r2!, {r1,r3-r6,sp}
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stmda r2!, {r1,r3-r6,sp}
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stmdb r2!, {r1,r3-r6,sp}
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