Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed.
llvm-svn: 106481
This commit is contained in:
Evan Cheng
parent
3f272b853f
commit
1fb4de8ec5
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@ -74,11 +74,14 @@ namespace {
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private:
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struct MemOpQueueEntry {
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int Offset;
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unsigned Reg;
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bool isKill;
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unsigned Position;
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MachineBasicBlock::iterator MBBI;
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bool Merged;
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MemOpQueueEntry(int o, int p, MachineBasicBlock::iterator i)
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: Offset(o), Position(p), MBBI(i), Merged(false) {}
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MemOpQueueEntry(int o, unsigned r, bool k, unsigned p,
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MachineBasicBlock::iterator i)
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: Offset(o), Reg(r), isKill(k), Position(p), MBBI(i), Merged(false) {}
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};
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typedef SmallVector<MemOpQueueEntry,8> MemOpQueue;
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typedef MemOpQueue::iterator MemOpQueueIter;
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@ -264,39 +267,53 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
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// MergeOpsUpdate - call MergeOps and update MemOps and merges accordingly on
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// success.
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void ARMLoadStoreOpt::
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MergeOpsUpdate(MachineBasicBlock &MBB,
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MemOpQueue &memOps,
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unsigned memOpsBegin,
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unsigned memOpsEnd,
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unsigned insertAfter,
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int Offset,
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unsigned Base,
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bool BaseKill,
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int Opcode,
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ARMCC::CondCodes Pred,
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unsigned PredReg,
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unsigned Scratch,
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DebugLoc dl,
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SmallVector<MachineBasicBlock::iterator, 4> &Merges) {
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void ARMLoadStoreOpt::MergeOpsUpdate(MachineBasicBlock &MBB,
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MemOpQueue &memOps,
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unsigned memOpsBegin, unsigned memOpsEnd,
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unsigned insertAfter, int Offset,
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unsigned Base, bool BaseKill,
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int Opcode,
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ARMCC::CondCodes Pred, unsigned PredReg,
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unsigned Scratch,
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DebugLoc dl,
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SmallVector<MachineBasicBlock::iterator, 4> &Merges) {
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// First calculate which of the registers should be killed by the merged
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// instruction.
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SmallVector<std::pair<unsigned, bool>, 8> Regs;
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const unsigned insertPos = memOps[insertAfter].Position;
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SmallSet<unsigned, 4> UnavailRegs;
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SmallSet<unsigned, 4> KilledRegs;
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DenseMap<unsigned, unsigned> Killer;
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for (unsigned i = 0; i < memOpsBegin; ++i) {
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if (memOps[i].Position < insertPos && memOps[i].isKill) {
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unsigned Reg = memOps[i].Reg;
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if (memOps[i].Merged)
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UnavailRegs.insert(Reg);
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else {
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KilledRegs.insert(Reg);
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Killer[Reg] = i;
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}
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}
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}
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for (unsigned i = memOpsEnd, e = memOps.size(); i != e; ++i) {
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if (memOps[i].Position < insertPos && memOps[i].isKill) {
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unsigned Reg = memOps[i].Reg;
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KilledRegs.insert(Reg);
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Killer[Reg] = i;
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}
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}
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SmallVector<std::pair<unsigned, bool>, 8> Regs;
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for (unsigned i = memOpsBegin; i < memOpsEnd; ++i) {
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const MachineOperand &MO = memOps[i].MBBI->getOperand(0);
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unsigned Reg = MO.getReg();
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bool isKill = MO.isKill();
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unsigned Reg = memOps[i].Reg;
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if (UnavailRegs.count(Reg))
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// Register is killed before and it's not easy / possible to update the
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// kill marker on already merged instructions. Abort.
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return;
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// If we are inserting the merged operation after an unmerged operation that
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// uses the same register, make sure to transfer any kill flag.
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for (unsigned j = memOpsEnd, e = memOps.size(); !isKill && j != e; ++j)
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if (memOps[j].Position<insertPos) {
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const MachineOperand &MOJ = memOps[j].MBBI->getOperand(0);
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if (MOJ.getReg() == Reg && MOJ.isKill())
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isKill = true;
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}
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bool isKill = memOps[i].isKill || KilledRegs.count(Reg);
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Regs.push_back(std::make_pair(Reg, isKill));
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}
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@ -311,13 +328,13 @@ MergeOpsUpdate(MachineBasicBlock &MBB,
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Merges.push_back(prior(Loc));
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for (unsigned i = memOpsBegin; i < memOpsEnd; ++i) {
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// Remove kill flags from any unmerged memops that come before insertPos.
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if (Regs[i-memOpsBegin].second)
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for (unsigned j = memOpsEnd, e = memOps.size(); j != e; ++j)
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if (memOps[j].Position<insertPos) {
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MachineOperand &MOJ = memOps[j].MBBI->getOperand(0);
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if (MOJ.getReg() == Regs[i-memOpsBegin].first && MOJ.isKill())
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MOJ.setIsKill(false);
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}
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if (Regs[i-memOpsBegin].second) {
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unsigned Reg = Regs[i-memOpsBegin].first;
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if (KilledRegs.count(Reg)) {
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unsigned j = Killer[Reg];
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memOps[j].MBBI->getOperand(0).setIsKill(false);
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}
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}
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MBB.erase(memOps[i].MBBI);
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memOps[i].Merged = true;
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}
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@ -910,6 +927,7 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
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if ((EvenRegNum & 1) == 0 && (EvenRegNum + 1) == OddRegNum)
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return false;
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MachineBasicBlock::iterator NewBBI = MBBI;
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bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8;
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bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;
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bool EvenDeadKill = isLd ?
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@ -954,6 +972,7 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
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getKillRegState(OddDeadKill) | getUndefRegState(OddUndef));
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++NumSTRD2STM;
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}
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NewBBI = llvm::prior(MBBI);
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} else {
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// Split into two instructions.
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assert((!isT2 || !OffReg) &&
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@ -974,6 +993,7 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
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OddReg, OddDeadKill, false,
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BaseReg, false, BaseUndef, OffReg, false, OffUndef,
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Pred, PredReg, TII, isT2);
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NewBBI = llvm::prior(MBBI);
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InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
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EvenReg, EvenDeadKill, false,
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BaseReg, BaseKill, BaseUndef, OffReg, OffKill, OffUndef,
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@ -990,6 +1010,7 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
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EvenReg, EvenDeadKill, EvenUndef,
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BaseReg, false, BaseUndef, OffReg, false, OffUndef,
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Pred, PredReg, TII, isT2);
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NewBBI = llvm::prior(MBBI);
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InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc,
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OddReg, OddDeadKill, OddUndef,
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BaseReg, BaseKill, BaseUndef, OffReg, OffKill, OffUndef,
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@ -1001,8 +1022,9 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
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++NumSTRD2STR;
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}
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MBBI = prior(MBBI);
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MBB.erase(MI);
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MBBI = NewBBI;
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return true;
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}
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return false;
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}
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@ -1035,6 +1057,9 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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if (isMemOp) {
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int Opcode = MBBI->getOpcode();
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unsigned Size = getLSMultipleTransferSize(MBBI);
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const MachineOperand &MO = MBBI->getOperand(0);
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unsigned Reg = MO.getReg();
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bool isKill = MO.isDef() ? false : MO.isKill();
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unsigned Base = MBBI->getOperand(1).getReg();
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unsigned PredReg = 0;
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ARMCC::CondCodes Pred = llvm::getInstrPredicate(MBBI, PredReg);
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@ -1056,7 +1081,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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CurrSize = Size;
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CurrPred = Pred;
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CurrPredReg = PredReg;
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MemOps.push_back(MemOpQueueEntry(Offset, Position, MBBI));
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MemOps.push_back(MemOpQueueEntry(Offset, Reg, isKill, Position, MBBI));
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NumMemOps++;
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Advance = true;
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} else {
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@ -1069,14 +1094,16 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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// No need to match PredReg.
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// Continue adding to the queue.
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if (Offset > MemOps.back().Offset) {
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MemOps.push_back(MemOpQueueEntry(Offset, Position, MBBI));
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MemOps.push_back(MemOpQueueEntry(Offset, Reg, isKill,
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Position, MBBI));
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NumMemOps++;
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Advance = true;
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} else {
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for (MemOpQueueIter I = MemOps.begin(), E = MemOps.end();
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I != E; ++I) {
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if (Offset < I->Offset) {
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MemOps.insert(I, MemOpQueueEntry(Offset, Position, MBBI));
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MemOps.insert(I, MemOpQueueEntry(Offset, Reg, isKill,
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Position, MBBI));
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NumMemOps++;
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Advance = true;
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break;
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@ -0,0 +1,148 @@
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; RUN: llc < %s -mtriple=armv7-apple-darwin -O3 -mcpu=arm1136jf-s
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; PR7421
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%struct.CONTENTBOX = type { i32, i32, i32, i32, i32 }
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%struct.FILE = type { i8* }
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%struct.tilebox = type { %struct.tilebox*, double, double, double, double, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
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%struct.UNCOMBOX = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
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%struct.cellbox = type { i8*, i32, i32, i32, [9 x i32], i32, i32, i32, i32, i32, i32, i32, double, double, double, double, double, i32, i32, %struct.CONTENTBOX*, %struct.UNCOMBOX*, [8 x %struct.tilebox*] }
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%struct.termbox = type { %struct.termbox*, i32, i32, i32, i32, i32 }
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@.str2708 = external constant [14 x i8], align 4 ; <[14 x i8]*> [#uses=1]
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define void @TW_oldinput(%struct.FILE* nocapture %fp) nounwind {
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entry:
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%xcenter = alloca i32, align 4 ; <i32*> [#uses=2]
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%0 = call i32 (%struct.FILE*, i8*, ...)* @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; <i32> [#uses=1]
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%1 = icmp eq i32 %0, 4 ; <i1> [#uses=1]
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br i1 %1, label %bb, label %return
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bb: ; preds = %bb445, %entry
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%2 = load %struct.cellbox** undef, align 4 ; <%struct.cellbox*> [#uses=2]
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%3 = getelementptr inbounds %struct.cellbox* %2, i32 0, i32 3 ; <i32*> [#uses=1]
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store i32 undef, i32* %3, align 4
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%4 = load i32* undef, align 4 ; <i32> [#uses=3]
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%5 = icmp eq i32 undef, 1 ; <i1> [#uses=1]
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br i1 %5, label %bb10, label %bb445
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bb10: ; preds = %bb
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br i1 undef, label %bb11, label %bb445
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bb11: ; preds = %bb10
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%6 = load %struct.tilebox** undef, align 4 ; <%struct.tilebox*> [#uses=3]
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%7 = load %struct.termbox** null, align 4 ; <%struct.termbox*> [#uses=1]
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%8 = getelementptr inbounds %struct.tilebox* %6, i32 0, i32 13 ; <i32*> [#uses=1]
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%9 = load i32* %8, align 4 ; <i32> [#uses=3]
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%10 = getelementptr inbounds %struct.tilebox* %6, i32 0, i32 15 ; <i32*> [#uses=1]
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%11 = load i32* %10, align 4 ; <i32> [#uses=1]
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br i1 false, label %bb12, label %bb13
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bb12: ; preds = %bb11
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unreachable
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bb13: ; preds = %bb11
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%iftmp.40.0.neg = sdiv i32 0, -2 ; <i32> [#uses=2]
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%12 = sub nsw i32 0, %9 ; <i32> [#uses=1]
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%13 = sitofp i32 %12 to double ; <double> [#uses=1]
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%14 = fdiv double %13, 0.000000e+00 ; <double> [#uses=1]
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%15 = fptosi double %14 to i32 ; <i32> [#uses=1]
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%iftmp.41.0.in = add i32 0, %15 ; <i32> [#uses=1]
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%iftmp.41.0.neg = sdiv i32 %iftmp.41.0.in, -2 ; <i32> [#uses=3]
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br i1 undef, label %bb43.loopexit, label %bb21
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bb21: ; preds = %bb13
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%16 = fptosi double undef to i32 ; <i32> [#uses=1]
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%17 = fsub double undef, 0.000000e+00 ; <double> [#uses=1]
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%not.460 = fcmp oge double %17, 5.000000e-01 ; <i1> [#uses=1]
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%18 = zext i1 %not.460 to i32 ; <i32> [#uses=1]
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%iftmp.42.0 = add i32 %16, %iftmp.41.0.neg ; <i32> [#uses=1]
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%19 = add i32 %iftmp.42.0, %18 ; <i32> [#uses=1]
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store i32 %19, i32* undef, align 4
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%20 = sub nsw i32 0, %9 ; <i32> [#uses=1]
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%21 = sitofp i32 %20 to double ; <double> [#uses=1]
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%22 = fdiv double %21, 0.000000e+00 ; <double> [#uses=2]
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%23 = fptosi double %22 to i32 ; <i32> [#uses=1]
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%24 = fsub double %22, undef ; <double> [#uses=1]
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%not.461 = fcmp oge double %24, 5.000000e-01 ; <i1> [#uses=1]
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%25 = zext i1 %not.461 to i32 ; <i32> [#uses=1]
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%iftmp.43.0 = add i32 %23, %iftmp.41.0.neg ; <i32> [#uses=1]
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%26 = add i32 %iftmp.43.0, %25 ; <i32> [#uses=1]
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%27 = getelementptr inbounds %struct.tilebox* %6, i32 0, i32 10 ; <i32*> [#uses=1]
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store i32 %26, i32* %27, align 4
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%28 = fptosi double undef to i32 ; <i32> [#uses=1]
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%iftmp.45.0 = add i32 %28, %iftmp.40.0.neg ; <i32> [#uses=1]
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%29 = add i32 %iftmp.45.0, 0 ; <i32> [#uses=1]
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store i32 %29, i32* undef, align 4
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br label %bb43.loopexit
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bb36: ; preds = %bb43.loopexit, %bb36
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%termptr.0478 = phi %struct.termbox* [ %42, %bb36 ], [ %7, %bb43.loopexit ] ; <%struct.termbox*> [#uses=1]
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%30 = load i32* undef, align 4 ; <i32> [#uses=1]
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%31 = sub nsw i32 %30, %9 ; <i32> [#uses=1]
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%32 = sitofp i32 %31 to double ; <double> [#uses=1]
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%33 = fdiv double %32, 0.000000e+00 ; <double> [#uses=1]
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%34 = fptosi double %33 to i32 ; <i32> [#uses=1]
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%iftmp.46.0 = add i32 %34, %iftmp.41.0.neg ; <i32> [#uses=1]
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%35 = add i32 %iftmp.46.0, 0 ; <i32> [#uses=1]
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store i32 %35, i32* undef, align 4
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%36 = sub nsw i32 0, %11 ; <i32> [#uses=1]
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%37 = sitofp i32 %36 to double ; <double> [#uses=1]
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%38 = fmul double %37, 0.000000e+00 ; <double> [#uses=1]
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%39 = fptosi double %38 to i32 ; <i32> [#uses=1]
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%iftmp.47.0 = add i32 %39, %iftmp.40.0.neg ; <i32> [#uses=1]
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%40 = add i32 %iftmp.47.0, 0 ; <i32> [#uses=1]
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store i32 %40, i32* undef, align 4
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%41 = getelementptr inbounds %struct.termbox* %termptr.0478, i32 0, i32 0 ; <%struct.termbox**> [#uses=1]
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%42 = load %struct.termbox** %41, align 4 ; <%struct.termbox*> [#uses=2]
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%43 = icmp eq %struct.termbox* %42, null ; <i1> [#uses=1]
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br i1 %43, label %bb52.loopexit, label %bb36
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bb43.loopexit: ; preds = %bb21, %bb13
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br i1 undef, label %bb52.loopexit, label %bb36
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bb52.loopexit: ; preds = %bb43.loopexit, %bb36
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%44 = icmp eq i32 %4, 0 ; <i1> [#uses=1]
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br i1 %44, label %bb.nph485, label %bb54
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bb54: ; preds = %bb52.loopexit
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switch i32 %4, label %bb62 [
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i32 2, label %bb56
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i32 3, label %bb57
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]
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bb56: ; preds = %bb54
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br label %bb62
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bb57: ; preds = %bb54
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br label %bb62
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bb62: ; preds = %bb57, %bb56, %bb54
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unreachable
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bb.nph485: ; preds = %bb52.loopexit
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br label %bb248
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bb248: ; preds = %bb322, %bb.nph485
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%45 = icmp eq i32 undef, %4 ; <i1> [#uses=1]
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br i1 %45, label %bb322, label %bb249
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bb249: ; preds = %bb248
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%46 = getelementptr inbounds %struct.cellbox* %2, i32 0, i32 21, i32 undef ; <%struct.tilebox**> [#uses=1]
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%47 = load %struct.tilebox** %46, align 4 ; <%struct.tilebox*> [#uses=1]
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%48 = getelementptr inbounds %struct.tilebox* %47, i32 0, i32 11 ; <i32*> [#uses=1]
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store i32 undef, i32* %48, align 4
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unreachable
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bb322: ; preds = %bb248
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br i1 undef, label %bb248, label %bb445
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bb445: ; preds = %bb322, %bb10, %bb
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%49 = call i32 (%struct.FILE*, i8*, ...)* @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; <i32> [#uses=1]
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%50 = icmp eq i32 %49, 4 ; <i1> [#uses=1]
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br i1 %50, label %bb, label %return
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return: ; preds = %bb445, %entry
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ret void
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}
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declare i32 @fscanf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind
|
||||
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Reference in New Issue