Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc.
llvm-svn: 39843
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@ -26,9 +26,9 @@ class Rf<bits<5> num, string n> : SparcReg<n> {
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let Num = num;
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let Num = num;
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}
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}
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// Rd - Slots in the FP register file for 64-bit floating-point values.
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// Rd - Slots in the FP register file for 64-bit floating-point values.
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class Rd<bits<5> num, string n, list<Register> aliases> : SparcReg<n> {
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class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
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let Num = num;
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let Num = num;
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let Aliases = aliases;
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let SubRegs = subregs;
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}
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}
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// Integer registers
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// Integer registers
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