Get rid of all symbolic loads. I now do gernate all relocations sequences
rather than relying on the assembler. Only a few more pseudo instructions left. Also merge load code paths. llvm-svn: 22305
This commit is contained in:
Andrew Lenharth
parent
8d9d9d7af0
commit
1ef3c0c798
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@ -92,9 +92,10 @@ namespace {
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setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
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setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
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setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
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setOperationAction(ISD::ZEXTLOAD, MVT::i1 , Expand);
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setOperationAction(ISD::ZEXTLOAD, MVT::i32 , Expand);
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setOperationAction(ISD::ZEXTLOAD, MVT::i1, Expand);
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setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
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setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
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setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
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@ -844,26 +845,6 @@ static long getLower16(long l)
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return l - h * IMM_MULT;
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}
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static unsigned GetSymVersion(unsigned opcode)
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{
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switch (opcode) {
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default: assert(0 && "unknown load or store"); return 0;
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case Alpha::LDQ: return Alpha::LDQ_SYM;
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case Alpha::LDS: return Alpha::LDS_SYM;
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case Alpha::LDT: return Alpha::LDT_SYM;
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case Alpha::LDL: return Alpha::LDL_SYM;
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case Alpha::LDBU: return Alpha::LDBU_SYM;
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case Alpha::LDWU: return Alpha::LDWU_SYM;
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case Alpha::LDW: return Alpha::LDW_SYM;
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case Alpha::LDB: return Alpha::LDB_SYM;
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case Alpha::STQ: return Alpha::STQ_SYM;
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case Alpha::STS: return Alpha::STS_SYM;
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case Alpha::STT: return Alpha::STT_SYM;
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case Alpha::STL: return Alpha::STL_SYM;
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case Alpha::STW: return Alpha::STW_SYM;
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case Alpha::STB: return Alpha::STB_SYM;
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}
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}
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static unsigned GetRelVersion(unsigned opcode)
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{
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switch (opcode) {
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@ -1212,74 +1193,6 @@ unsigned AlphaISel::SelectExprFP(SDOperand N, unsigned Result)
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BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
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return Result;
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case ISD::CopyFromReg:
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{
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// Make sure we generate both values.
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if (Result != notIn)
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ExprMap[N.getValue(1)] = notIn; // Generate the token
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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SDOperand Chain = N.getOperand(0);
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Select(Chain);
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unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
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//std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
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BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
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return Result;
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}
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case ISD::LOAD:
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{
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// Make sure we generate both values.
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if (Result != notIn)
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ExprMap[N.getValue(1)] = notIn; // Generate the token
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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DestType = N.getValue(0).getValueType();
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SDOperand Chain = N.getOperand(0);
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SDOperand Address = N.getOperand(1);
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Select(Chain);
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Opc = DestType == MVT::f64 ? Alpha::LDT : Alpha::LDS;
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if (EnableAlphaLSMark)
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{
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int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))
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->getValue());
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int j = getFunctionOffset(BB->getParent()->getFunction());
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BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
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}
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if (Address.getOpcode() == ISD::GlobalAddress) {
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AlphaLowering.restoreGP(BB);
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Opc = GetSymVersion(Opc);
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has_sym = true;
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BuildMI(BB, Opc, 1, Result)
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.addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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AlphaLowering.restoreGP(BB);
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Opc = GetRelVersion(Opc);
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has_sym = true;
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Tmp1 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CP->getIndex())
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.addReg(Alpha::R29);
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BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CP->getIndex())
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.addReg(Tmp1);
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}
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else if(Address.getOpcode() == ISD::FrameIndex) {
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BuildMI(BB, Opc, 2, Result)
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.addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
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.addReg(Alpha::F31);
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} else {
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long offset;
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SelectAddr(Address, Tmp1, offset);
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BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
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}
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return Result;
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}
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case ISD::ConstantFP:
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if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
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if (CN->isExactlyValue(+0.0)) {
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@ -1323,63 +1236,6 @@ unsigned AlphaISel::SelectExprFP(SDOperand N, unsigned Result)
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}
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return Result;
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case ISD::EXTLOAD:
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{
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//include a conversion sequence for float loads to double
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if (Result != notIn)
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ExprMap[N.getValue(1)] = notIn; // Generate the token
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else
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Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
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Tmp1 = MakeReg(MVT::f32);
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assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::f32 &&
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"EXTLOAD not from f32");
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assert(Node->getValueType(0) == MVT::f64 && "EXTLOAD not to f64");
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SDOperand Chain = N.getOperand(0);
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SDOperand Address = N.getOperand(1);
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Select(Chain);
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if (EnableAlphaLSMark)
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{
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int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))
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->getValue());
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int j = getFunctionOffset(BB->getParent()->getFunction());
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BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
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}
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if (Address.getOpcode() == ISD::GlobalAddress) {
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AlphaLowering.restoreGP(BB);
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has_sym = true;
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BuildMI(BB, Alpha::LDS_SYM, 1, Tmp1)
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.addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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else if (ConstantPoolSDNode *CP =
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dyn_cast<ConstantPoolSDNode>(N.getOperand(1)))
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{
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AlphaLowering.restoreGP(BB);
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has_sym = true;
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Tmp2 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::LDAHr, 2, Tmp2).addConstantPoolIndex(CP->getIndex())
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.addReg(Alpha::R29);
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BuildMI(BB, Alpha::LDSr, 2, Tmp1).addConstantPoolIndex(CP->getIndex())
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.addReg(Tmp2);
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}
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else if(Address.getOpcode() == ISD::FrameIndex) {
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Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
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BuildMI(BB, Alpha::LDS, 2, Tmp1)
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.addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
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.addReg(Alpha::F31);
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} else {
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long offset;
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SelectAddr(Address, Tmp2, offset);
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BuildMI(BB, Alpha::LDS, 1, Tmp1).addImm(offset).addReg(Tmp2);
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}
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BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
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return Result;
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}
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case ISD::SINT_TO_FP:
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{
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assert (N.getOperand(0).getValueType() == MVT::i64
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@ -1425,17 +1281,10 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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}
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}
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if ((DestType == MVT::f64 || DestType == MVT::f32 ||
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(
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(opcode == ISD::LOAD || opcode == ISD::CopyFromReg ||
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opcode == ISD::EXTLOAD) &&
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(N.getValue(0).getValueType() == MVT::f32 ||
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N.getValue(0).getValueType() == MVT::f64)
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))
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&& opcode != ISD::CALL && opcode != ISD::TAILCALL
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)
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if ((DestType == MVT::f64 || DestType == MVT::f32)
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&& opcode != ISD::CALL && opcode != ISD::TAILCALL)
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return SelectExprFP(N, Result);
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switch (opcode) {
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default:
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Node->dump();
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@ -1550,10 +1399,15 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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SDOperand Address = N.getOperand(1);
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Select(Chain);
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assert(Node->getValueType(0) == MVT::i64 &&
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"Unknown type to sign extend to.");
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bool fpext = true;
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if (opcode == ISD::LOAD)
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Opc = Alpha::LDQ;
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switch (Node->getValueType(0)) {
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default: Node->dump(); assert(0 && "Bad load!");
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case MVT::i64: Opc = Alpha::LDQ; break;
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case MVT::f64: Opc = Alpha::LDT; break;
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case MVT::f32: Opc = Alpha::LDS; break;
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}
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else
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switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
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default: Node->dump(); assert(0 && "Bad sign extend!");
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@ -1566,38 +1420,50 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
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}
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if (EnableAlphaLSMark)
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{
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int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))
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->getValue());
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int j = getFunctionOffset(BB->getParent()->getFunction());
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BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
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int i = 0, j = 0;
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if (EnableAlphaLSMark) {
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i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))
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->getValue());
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j = getFunctionOffset(BB->getParent()->getFunction());
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}
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if (Address.getOpcode() == ISD::GlobalAddress) {
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if (GlobalAddressSDNode *GASD =
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dyn_cast<GlobalAddressSDNode>(Address)) {
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if (GASD->getGlobal()->isExternal()) {
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Tmp1 = SelectExpr(Address);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
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BuildMI(BB, Opc, 2, Result).addImm(0).addReg(Tmp1);
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} else {
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Tmp1 = MakeReg(MVT::i64);
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::LDAHr, 2, Tmp1)
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.addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
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BuildMI(BB, GetRelVersion(Opc), 2, Result)
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.addGlobalAddress(GASD->getGlobal()).addReg(Tmp1);
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}
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} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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AlphaLowering.restoreGP(BB);
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Opc = GetSymVersion(Opc);
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has_sym = true;
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BuildMI(BB, Opc, 1, Result)
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.addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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AlphaLowering.restoreGP(BB);
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Opc = GetRelVersion(Opc);
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has_sym = true;
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Tmp1 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CP->getIndex())
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.addReg(Alpha::R29);
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BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CP->getIndex())
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.addReg(Tmp1);
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}
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else if(Address.getOpcode() == ISD::FrameIndex) {
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
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BuildMI(BB, GetRelVersion(Opc), 2, Result)
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.addConstantPoolIndex(CP->getIndex()).addReg(Tmp1);
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} else if(Address.getOpcode() == ISD::FrameIndex) {
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
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BuildMI(BB, Opc, 2, Result)
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.addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
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.addReg(Alpha::F31);
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} else {
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long offset;
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SelectAddr(Address, Tmp1, offset);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
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BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
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}
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return Result;
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@ -1606,7 +1472,11 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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case ISD::GlobalAddress:
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AlphaLowering.restoreGP(BB);
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has_sym = true;
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BuildMI(BB, Alpha::LDQrl, 2, Result)
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 3).addImm(0).addImm(0).addImm(getUID());
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BuildMI(BB, Alpha::LDQl, 2, Result)
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.addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal())
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.addReg(Alpha::R29);
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return Result;
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@ -1922,7 +1792,10 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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Select(Chain);
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unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
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//std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
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BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r);
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if (DestType == MVT::f32 || DestType == MVT::f64)
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BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
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else
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BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r);
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return Result;
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}
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@ -2422,32 +2295,24 @@ void AlphaISel::Select(SDOperand N) {
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}
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}
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if (EnableAlphaLSMark)
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{
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int i =
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int i = 0, j = 0;
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if (EnableAlphaLSMark) {
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i =
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getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(3))->getValue());
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int j = getFunctionOffset(BB->getParent()->getFunction());
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BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
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j = getFunctionOffset(BB->getParent()->getFunction());
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}
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if (Address.getOpcode() == ISD::GlobalAddress)
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{
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AlphaLowering.restoreGP(BB);
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Opc = GetSymVersion(Opc);
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has_sym = true;
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BuildMI(BB, Opc, 2).addReg(Tmp1)
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.addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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else if(Address.getOpcode() == ISD::FrameIndex)
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{
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if(Address.getOpcode() == ISD::FrameIndex) {
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
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BuildMI(BB, Opc, 3).addReg(Tmp1)
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.addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
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.addReg(Alpha::F31);
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}
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else
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{
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} else {
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long offset;
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SelectAddr(Address, Tmp2, offset);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
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BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
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}
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return;
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@ -53,30 +53,6 @@ let isCall = 1,
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Uses = [R29] in
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def CALL : PseudoInstAlpha< (ops s64imm:$TARGET), "jsr $TARGET">; //Jump to subroutine
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//These are evil as they get expanded into multiple instructions to take care of reallocation
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let Uses = [R29], Defs = [R28] in {
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def LDQ_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldq $RA,$DISP">; //Load quadword
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def LDS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lds $RA,$DISP">; //Load float
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def LDT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldt $RA,$DISP">; //Load double
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def LDL_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldl $RA,$DISP">; // Load sign-extended longword
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def LDBU_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldbu $RA,$DISP">; //Load zero-extended byte
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def LDWU_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldwu $RA,$DISP">; //Load zero-extended word
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def LDW_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldw $RA,$DISP">; // Load sign-extended word
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def LDB_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldb $RA,$DISP">; //Load byte
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def LDW : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldw $RA,$DISP($RB)">; // Load sign-extended word
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def LDB : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldb $RA,$DISP($RB)">; //Load byte
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def STB_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stb $RA,$DISP">; // Store byte
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def STW_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stw $RA,$DISP">; // Store word
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def STL_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stl $RA,$DISP">; // Store longword
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def STQ_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stq $RA,$DISP">; //Store quadword
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def STS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "sts $RA,$DISP">; //store float
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def STT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "stt $RA,$DISP">; //store double
|
||||
}
|
||||
|
||||
|
||||
//RESULTS of these go to R27
|
||||
//These are also evil as the assembler expands them into calls
|
||||
let Uses = [R29],
|
||||
|
|
@ -357,21 +333,22 @@ def LDA : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "lda $RA,$DISP($RB
|
|||
def LDAH : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldah $RA,$DISP($RB)">; //Load address high
|
||||
|
||||
|
||||
//Loads, int, Rellocated form
|
||||
//Loads, int, Rellocated Low form
|
||||
def LDLr : MForm<0x28, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldl $RA,$DISP($RB) !gprellow">; // Load sign-extended longword
|
||||
def LDQr : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !gprellow">; //Load quadword
|
||||
def LDBUr : MForm<0x0A, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldbu $RA,$DISP($RB) !gprellow">; //Load zero-extended byte
|
||||
def LDWUr : MForm<0x0C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldwu $RA,$DISP($RB) !gprellow">; //Load zero-extended word
|
||||
def LDQrl : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !literal">; //Load quadword
|
||||
|
||||
//Loads, float, Rellocated form
|
||||
//Loads, float, Rellocated Low form
|
||||
def LDSr : MForm<0x22, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "lds $RA,$DISP($RB) !gprellow">; //Load S_floating
|
||||
def LDTr : MForm<0x23, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldt $RA,$DISP($RB) !gprellow">; //Load T_floating
|
||||
|
||||
//Load address, rellocated form
|
||||
//Load address, rellocated low and high form
|
||||
def LDAr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "lda $RA,$DISP($RB) !gprellow">; //Load address
|
||||
def LDAHr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldah $RA,$DISP($RB) !gprelhigh">; //Load address high
|
||||
|
||||
//Load quad, rellocated literal form
|
||||
def LDQl : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !literal">; //Load quadword
|
||||
|
||||
//Branches, int
|
||||
def BEQ : BForm<0x39, (ops GPRC:$RA, s21imm:$DISP), "beq $RA,$DISP">; //Branch if = zero
|
||||
|
|
|
|||
|
|
@ -82,9 +82,13 @@ def F30 : FPR<30, "$f30">; def F31 : FPR<31, "$f31">;
|
|||
def GPRC : RegisterClass<i64, 64,
|
||||
// Volatile
|
||||
[R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
|
||||
R23, R24, R25, R26, R27,
|
||||
R23, R24, R25,
|
||||
//Special meaning, but volatile
|
||||
R27, //procedure address
|
||||
R26, //return address
|
||||
R29, //global offset table address
|
||||
// Non-volatile
|
||||
R9, R10, R11, R12, R13, R14, R29 ]>;
|
||||
R9, R10, R11, R12, R13, R14 ]>;
|
||||
// Note: R28 is reserved for the assembler
|
||||
|
||||
// Don't allocate 15, 29, 30, 31
|
||||
|
|
|
|||
Loading…
Reference in New Issue