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[mips] Disable the TImode shift libcalls for 32-bit targets. 

Summary:
The o32 ABI doesn't not support the TImode helpers. For the time being,
disable just the shift libcalls as they break recursive builds on MIPS.

Reviewers: sdardis

Subscribers: llvm-commits, sdardis

Differential Revision: https://reviews.llvm.org/D24259

llvm-svn: 280798
This commit is contained in:
Vasileios Kalintiris 2016-09-07 10:01:18 +00:00
parent 8825a5c6ef
commit 1ed49fd384
4 changed files with 16 additions and 9 deletions
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7
llvm/lib/Target/Mips/MipsISelLowering.cpp
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@ -426,6 +426,13 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
setTargetDAGCombine(ISD::ADD); setTargetDAGCombine(ISD::ADD);
setTargetDAGCombine(ISD::AssertZext); setTargetDAGCombine(ISD::AssertZext);
if (ABI.IsO32()) {
// These libcalls are not available in 32-bit.
setLibcallName(RTLIB::SHL_I128, nullptr);
setLibcallName(RTLIB::SRL_I128, nullptr);
setLibcallName(RTLIB::SRA_I128, nullptr);
}
setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
// The arguments on the stack are defined in terms of 4-byte slots on O32 // The arguments on the stack are defined in terms of 4-byte slots on O32

6
llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
View File

@ -162,7 +162,9 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
entry: entry:
; ALL-LABEL: ashr_i128: ; ALL-LABEL: ashr_i128:
; GP32: lw $25, %call16(__ashrti3)($gp) ; o32 shouldn't use TImode helpers.
; GP32-NOT: lw $25, %call16(__ashrti3)($gp)
; MM-NOT: lw $25, %call16(__ashrti3)($2)
; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsrav $[[T1:[0-9]+]], $4, $7 ; M3: dsrav $[[T1:[0-9]+]], $4, $7
@ -213,8 +215,6 @@ entry:
; 64R6: jr $ra ; 64R6: jr $ra
; 64R6: or $3, $[[T13]], $[[T12]] ; 64R6: or $3, $[[T13]], $[[T12]]
; MM: lw $25, %call16(__ashrti3)($2)
%r = ashr i128 %a, %b %r = ashr i128 %a, %b
ret i128 %r ret i128 %r
} }

6
llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
View File

@ -153,7 +153,9 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
entry: entry:
; ALL-LABEL: lshr_i128: ; ALL-LABEL: lshr_i128:
; GP32: lw $25, %call16(__lshrti3)($gp) ; o32 shouldn't use TImode helpers.
; GP32-NOT: lw $25, %call16(__lshrti3)($gp)
; MM-NOT: lw $25, %call16(__lshrti3)($2)
; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsrlv $[[T1:[0-9]+]], $4, $7 ; M3: dsrlv $[[T1:[0-9]+]], $4, $7
@ -200,8 +202,6 @@ entry:
; 64R6: jr $ra ; 64R6: jr $ra
; 64R6: seleqz $2, $[[T9]], $[[T7]] ; 64R6: seleqz $2, $[[T9]], $[[T7]]
; MM: lw $25, %call16(__lshrti3)($2)
%r = lshr i128 %a, %b %r = lshr i128 %a, %b
ret i128 %r ret i128 %r
} }

6
llvm/test/CodeGen/Mips/llvm-ir/shl.ll
View File

@ -169,7 +169,9 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
entry: entry:
; ALL-LABEL: shl_i128: ; ALL-LABEL: shl_i128:
; GP32: lw $25, %call16(__ashlti3)($gp) ; o32 shouldn't use TImode helpers.
; GP32-NOT: lw $25, %call16(__ashlti3)($gp)
; MM-NOT: lw $25, %call16(__ashlti3)($2)
; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsllv $[[T1:[0-9]+]], $5, $7 ; M3: dsllv $[[T1:[0-9]+]], $5, $7
@ -216,8 +218,6 @@ entry:
; 64R6: jr $ra ; 64R6: jr $ra
; 64R6: seleqz $3, $[[T9]], $[[T7]] ; 64R6: seleqz $3, $[[T9]], $[[T7]]
; MM: lw $25, %call16(__ashlti3)($2)
%r = shl i128 %a, %b %r = shl i128 %a, %b
ret i128 %r ret i128 %r
} }