[mips] Disable the TImode shift libcalls for 32-bit targets.
Summary: The o32 ABI doesn't not support the TImode helpers. For the time being, disable just the shift libcalls as they break recursive builds on MIPS. Reviewers: sdardis Subscribers: llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D24259 llvm-svn: 280798
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@ -426,6 +426,13 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
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setTargetDAGCombine(ISD::ADD);
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setTargetDAGCombine(ISD::ADD);
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setTargetDAGCombine(ISD::AssertZext);
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setTargetDAGCombine(ISD::AssertZext);
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if (ABI.IsO32()) {
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// These libcalls are not available in 32-bit.
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setLibcallName(RTLIB::SHL_I128, nullptr);
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setLibcallName(RTLIB::SRL_I128, nullptr);
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setLibcallName(RTLIB::SRA_I128, nullptr);
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}
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setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
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setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
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// The arguments on the stack are defined in terms of 4-byte slots on O32
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// The arguments on the stack are defined in terms of 4-byte slots on O32
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@ -162,7 +162,9 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
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entry:
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entry:
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; ALL-LABEL: ashr_i128:
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; ALL-LABEL: ashr_i128:
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; GP32: lw $25, %call16(__ashrti3)($gp)
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; o32 shouldn't use TImode helpers.
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; GP32-NOT: lw $25, %call16(__ashrti3)($gp)
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; MM-NOT: lw $25, %call16(__ashrti3)($2)
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; M3: sll $[[T0:[0-9]+]], $7, 0
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; M3: sll $[[T0:[0-9]+]], $7, 0
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; M3: dsrav $[[T1:[0-9]+]], $4, $7
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; M3: dsrav $[[T1:[0-9]+]], $4, $7
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@ -213,8 +215,6 @@ entry:
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; 64R6: jr $ra
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; 64R6: jr $ra
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; 64R6: or $3, $[[T13]], $[[T12]]
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; 64R6: or $3, $[[T13]], $[[T12]]
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; MM: lw $25, %call16(__ashrti3)($2)
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%r = ashr i128 %a, %b
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%r = ashr i128 %a, %b
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ret i128 %r
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ret i128 %r
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}
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}
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@ -153,7 +153,9 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
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entry:
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entry:
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; ALL-LABEL: lshr_i128:
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; ALL-LABEL: lshr_i128:
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; GP32: lw $25, %call16(__lshrti3)($gp)
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; o32 shouldn't use TImode helpers.
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; GP32-NOT: lw $25, %call16(__lshrti3)($gp)
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; MM-NOT: lw $25, %call16(__lshrti3)($2)
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; M3: sll $[[T0:[0-9]+]], $7, 0
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; M3: sll $[[T0:[0-9]+]], $7, 0
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; M3: dsrlv $[[T1:[0-9]+]], $4, $7
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; M3: dsrlv $[[T1:[0-9]+]], $4, $7
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@ -200,8 +202,6 @@ entry:
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; 64R6: jr $ra
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; 64R6: jr $ra
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; 64R6: seleqz $2, $[[T9]], $[[T7]]
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; 64R6: seleqz $2, $[[T9]], $[[T7]]
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; MM: lw $25, %call16(__lshrti3)($2)
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%r = lshr i128 %a, %b
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%r = lshr i128 %a, %b
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ret i128 %r
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ret i128 %r
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}
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}
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@ -169,7 +169,9 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
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entry:
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entry:
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; ALL-LABEL: shl_i128:
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; ALL-LABEL: shl_i128:
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; GP32: lw $25, %call16(__ashlti3)($gp)
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; o32 shouldn't use TImode helpers.
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; GP32-NOT: lw $25, %call16(__ashlti3)($gp)
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; MM-NOT: lw $25, %call16(__ashlti3)($2)
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; M3: sll $[[T0:[0-9]+]], $7, 0
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; M3: sll $[[T0:[0-9]+]], $7, 0
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; M3: dsllv $[[T1:[0-9]+]], $5, $7
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; M3: dsllv $[[T1:[0-9]+]], $5, $7
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@ -216,8 +218,6 @@ entry:
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; 64R6: jr $ra
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; 64R6: jr $ra
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; 64R6: seleqz $3, $[[T9]], $[[T7]]
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; 64R6: seleqz $3, $[[T9]], $[[T7]]
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; MM: lw $25, %call16(__ashlti3)($2)
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%r = shl i128 %a, %b
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%r = shl i128 %a, %b
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ret i128 %r
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ret i128 %r
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}
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}
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