[Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly.
llvm-svn: 239477
This commit is contained in:
Colin LeMahieu
parent
cc01359cfe
commit
1e9d1d768c
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@ -69,6 +69,33 @@ static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op,
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raw_ostream &os);
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static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst);
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static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static const uint16_t IntRegDecoderTable[] = {
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Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
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Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
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@ -356,6 +383,97 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(
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return Result;
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}
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static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<16>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<12>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<11>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<12>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<13>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<14>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<10>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/,
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const void *Decoder) {
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uint64_t imm = SignExtend64<8>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<6>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<4>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<5>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<6>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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uint64_t imm = SignExtend64<7>(tmp);
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MI.addOperand(MCOperand::createImm(imm));
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return MCDisassembler::Success;
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}
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// These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td
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enum subInstBinaryValues {
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V4_SA1_addi_BITS = 0x0000,
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@ -7,32 +7,24 @@
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//
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//===----------------------------------------------------------------------===//
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def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; }
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def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; }
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def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; }
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def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; }
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// Immediate operands.
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let PrintMethod = "printImmOperand" in {
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// f32Ext type is used to identify constant extended floating point immediates.
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def f32Ext : Operand<f32>;
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def s32Imm : Operand<i32>;
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def s26_6Imm : Operand<i32>;
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def s16Imm : Operand<i32>;
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def s12Imm : Operand<i32>;
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def s11Imm : Operand<i32>;
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def s11_0Imm : Operand<i32>;
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def s11_1Imm : Operand<i32>;
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def s11_2Imm : Operand<i32>;
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def s11_3Imm : Operand<i32>;
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def s10Imm : Operand<i32>;
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def s9Imm : Operand<i32>;
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def m9Imm : Operand<i32>;
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def s8Imm : Operand<i32>;
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def s8Imm64 : Operand<i64>;
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def s6Imm : Operand<i32>;
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def s6_3Imm : Operand<i32>;
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def s4Imm : Operand<i32>;
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def s4_0Imm : Operand<i32>;
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def s4_1Imm : Operand<i32>;
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def s4_2Imm : Operand<i32>;
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def s4_3Imm : Operand<i32>;
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def s4_0Imm : Operand<i32> { let DecoderMethod = "s4_0ImmDecoder"; }
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def s4_1Imm : Operand<i32> { let DecoderMethod = "s4_1ImmDecoder"; }
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def s4_2Imm : Operand<i32> { let DecoderMethod = "s4_2ImmDecoder"; }
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def s4_3Imm : Operand<i32> { let DecoderMethod = "s4_3ImmDecoder"; }
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def u64Imm : Operand<i64>;
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def u32Imm : Operand<i32>;
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def u26_6Imm : Operand<i32>;
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@ -446,17 +438,18 @@ def SetClr3ImmPred : PatLeaf<(i32 imm), [{
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// Extendable immediate operands.
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let PrintMethod = "printExtOperand" in {
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def s16Ext : Operand<i32>;
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def s12Ext : Operand<i32>;
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def s10Ext : Operand<i32>;
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def s9Ext : Operand<i32>;
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def s8Ext : Operand<i32>;
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def f32Ext : Operand<f32>;
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def s16Ext : Operand<i32> { let DecoderMethod = "s16ImmDecoder"; }
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def s12Ext : Operand<i32> { let DecoderMethod = "s12ImmDecoder"; }
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def s11_0Ext : Operand<i32> { let DecoderMethod = "s11_0ImmDecoder"; }
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def s11_1Ext : Operand<i32> { let DecoderMethod = "s11_1ImmDecoder"; }
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def s11_2Ext : Operand<i32> { let DecoderMethod = "s11_2ImmDecoder"; }
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def s11_3Ext : Operand<i32> { let DecoderMethod = "s11_3ImmDecoder"; }
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def s10Ext : Operand<i32> { let DecoderMethod = "s10ImmDecoder"; }
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def s9Ext : Operand<i32> { let DecoderMethod = "s90ImmDecoder"; }
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def s8Ext : Operand<i32> { let DecoderMethod = "s8ImmDecoder"; }
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def s7Ext : Operand<i32>;
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def s6Ext : Operand<i32>;
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def s11_0Ext : Operand<i32>;
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def s11_1Ext : Operand<i32>;
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def s11_2Ext : Operand<i32>;
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def s11_3Ext : Operand<i32>;
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def s6Ext : Operand<i32> { let DecoderMethod = "s6_0ImmDecoder"; }
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def u6Ext : Operand<i32>;
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def u7Ext : Operand<i32>;
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def u8Ext : Operand<i32>;
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@ -17,11 +17,14 @@
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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using namespace Hexagon;
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#define DEBUG_TYPE "hexagon-asm-backend"
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namespace {
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class HexagonAsmBackend : public MCAsmBackend {
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@ -278,8 +281,26 @@ public:
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llvm_unreachable("relaxInstruction() unimplemented");
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}
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bool writeNopData(uint64_t /*Count*/,
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MCObjectWriter * /*OW*/) const override {
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bool writeNopData(uint64_t Count,
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MCObjectWriter * OW) const override {
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static const uint32_t Nopcode = 0x7f000000, // Hard-coded NOP.
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ParseIn = 0x00004000, // In packet parse-bits.
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ParseEnd = 0x0000c000; // End of packet parse-bits.
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while(Count % HEXAGON_INSTR_SIZE) {
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DEBUG(dbgs() << "Alignment not a multiple of the instruction size:" <<
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Count % HEXAGON_INSTR_SIZE << "/" << HEXAGON_INSTR_SIZE << "\n");
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--Count;
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OW->write8(0);
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}
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while(Count) {
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Count -= HEXAGON_INSTR_SIZE;
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// Close the packet whenever a multiple of the maximum packet size remains
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uint32_t ParseBits = (Count % (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE))?
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ParseIn: ParseEnd;
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OW->write32(Nopcode | ParseBits);
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}
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return true;
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}
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};
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@ -38,311 +38,209 @@ HexagonELFObjectWriter::HexagonELFObjectWriter(uint8_t OSABI, StringRef C)
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/*HasRelocationAddend*/ true),
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CPU(C) {}
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unsigned HexagonELFObjectWriter::GetRelocType(MCValue const &/*Target*/,
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unsigned HexagonELFObjectWriter::GetRelocType(MCValue const & /*Target*/,
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MCFixup const &Fixup,
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bool IsPCRel) const {
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// determine the type of the relocation
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unsigned Type = (unsigned)ELF::R_HEX_NONE;
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unsigned Kind = (unsigned)Fixup.getKind();
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switch (Kind) {
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default:
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DEBUG(dbgs() << "unrecognized relocation " << Fixup.getKind() << "\n");
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llvm_unreachable("Unimplemented Fixup kind!");
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break;
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case FK_Data_4:
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Type = (IsPCRel) ? ELF::R_HEX_32_PCREL : ELF::R_HEX_32;
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break;
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case FK_PCRel_4:
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Type = ELF::R_HEX_32_PCREL;
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break;
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case FK_Data_2:
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Type = ELF::R_HEX_16;
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break;
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case FK_Data_1:
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Type = ELF::R_HEX_8;
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break;
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case fixup_Hexagon_B22_PCREL:
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Type = ELF::R_HEX_B22_PCREL;
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break;
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case fixup_Hexagon_B15_PCREL:
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Type = ELF::R_HEX_B15_PCREL;
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break;
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case fixup_Hexagon_B7_PCREL:
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Type = ELF::R_HEX_B7_PCREL;
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break;
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case fixup_Hexagon_LO16:
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Type = ELF::R_HEX_LO16;
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break;
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case fixup_Hexagon_HI16:
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Type = ELF::R_HEX_HI16;
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break;
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case fixup_Hexagon_32:
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Type = ELF::R_HEX_32;
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break;
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case fixup_Hexagon_16:
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Type = ELF::R_HEX_16;
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break;
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case fixup_Hexagon_8:
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Type = ELF::R_HEX_8;
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break;
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case fixup_Hexagon_GPREL16_0:
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Type = ELF::R_HEX_GPREL16_0;
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break;
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case fixup_Hexagon_GPREL16_1:
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Type = ELF::R_HEX_GPREL16_1;
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break;
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case fixup_Hexagon_GPREL16_2:
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Type = ELF::R_HEX_GPREL16_2;
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break;
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case fixup_Hexagon_GPREL16_3:
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Type = ELF::R_HEX_GPREL16_3;
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break;
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case fixup_Hexagon_HL16:
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Type = ELF::R_HEX_HL16;
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break;
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case fixup_Hexagon_B13_PCREL:
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Type = ELF::R_HEX_B13_PCREL;
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break;
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case fixup_Hexagon_B9_PCREL:
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Type = ELF::R_HEX_B9_PCREL;
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break;
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case fixup_Hexagon_B32_PCREL_X:
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Type = ELF::R_HEX_B32_PCREL_X;
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break;
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case fixup_Hexagon_32_6_X:
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Type = ELF::R_HEX_32_6_X;
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break;
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case fixup_Hexagon_B22_PCREL_X:
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Type = ELF::R_HEX_B22_PCREL_X;
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break;
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case fixup_Hexagon_B15_PCREL_X:
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Type = ELF::R_HEX_B15_PCREL_X;
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break;
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case fixup_Hexagon_B13_PCREL_X:
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Type = ELF::R_HEX_B13_PCREL_X;
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break;
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case fixup_Hexagon_B9_PCREL_X:
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Type = ELF::R_HEX_B9_PCREL_X;
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break;
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case fixup_Hexagon_B7_PCREL_X:
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Type = ELF::R_HEX_B7_PCREL_X;
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break;
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case fixup_Hexagon_16_X:
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Type = ELF::R_HEX_16_X;
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break;
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case fixup_Hexagon_12_X:
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Type = ELF::R_HEX_12_X;
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break;
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case fixup_Hexagon_11_X:
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Type = ELF::R_HEX_11_X;
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break;
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case fixup_Hexagon_10_X:
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Type = ELF::R_HEX_10_X;
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break;
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case fixup_Hexagon_9_X:
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Type = ELF::R_HEX_9_X;
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break;
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case fixup_Hexagon_8_X:
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Type = ELF::R_HEX_8_X;
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break;
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case fixup_Hexagon_7_X:
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Type = ELF::R_HEX_7_X;
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break;
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case fixup_Hexagon_6_X:
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Type = ELF::R_HEX_6_X;
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break;
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case fixup_Hexagon_32_PCREL:
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Type = ELF::R_HEX_32_PCREL;
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break;
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case fixup_Hexagon_COPY:
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Type = ELF::R_HEX_COPY;
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break;
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case fixup_Hexagon_GLOB_DAT:
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Type = ELF::R_HEX_GLOB_DAT;
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break;
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case fixup_Hexagon_JMP_SLOT:
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Type = ELF::R_HEX_JMP_SLOT;
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break;
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case fixup_Hexagon_RELATIVE:
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Type = ELF::R_HEX_RELATIVE;
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break;
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case fixup_Hexagon_PLT_B22_PCREL:
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Type = ELF::R_HEX_PLT_B22_PCREL;
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break;
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case fixup_Hexagon_GOTREL_LO16:
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Type = ELF::R_HEX_GOTREL_LO16;
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break;
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case fixup_Hexagon_GOTREL_HI16:
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Type = ELF::R_HEX_GOTREL_HI16;
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break;
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case fixup_Hexagon_GOTREL_32:
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Type = ELF::R_HEX_GOTREL_32;
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break;
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case fixup_Hexagon_GOT_LO16:
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Type = ELF::R_HEX_GOT_LO16;
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break;
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case fixup_Hexagon_GOT_HI16:
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Type = ELF::R_HEX_GOT_HI16;
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break;
|
||||
case fixup_Hexagon_GOT_32:
|
||||
Type = ELF::R_HEX_GOT_32;
|
||||
break;
|
||||
case fixup_Hexagon_GOT_16:
|
||||
Type = ELF::R_HEX_GOT_16;
|
||||
break;
|
||||
case fixup_Hexagon_DTPMOD_32:
|
||||
Type = ELF::R_HEX_DTPMOD_32;
|
||||
break;
|
||||
case fixup_Hexagon_DTPREL_LO16:
|
||||
Type = ELF::R_HEX_DTPREL_LO16;
|
||||
break;
|
||||
case fixup_Hexagon_DTPREL_HI16:
|
||||
Type = ELF::R_HEX_DTPREL_HI16;
|
||||
break;
|
||||
case fixup_Hexagon_DTPREL_32:
|
||||
Type = ELF::R_HEX_DTPREL_32;
|
||||
break;
|
||||
case fixup_Hexagon_DTPREL_16:
|
||||
Type = ELF::R_HEX_DTPREL_16;
|
||||
break;
|
||||
case fixup_Hexagon_GD_PLT_B22_PCREL:
|
||||
Type = ELF::R_HEX_GD_PLT_B22_PCREL;
|
||||
break;
|
||||
case fixup_Hexagon_LD_PLT_B22_PCREL:
|
||||
Type = ELF::R_HEX_LD_PLT_B22_PCREL;
|
||||
break;
|
||||
case fixup_Hexagon_GD_GOT_LO16:
|
||||
Type = ELF::R_HEX_GD_GOT_LO16;
|
||||
break;
|
||||
case fixup_Hexagon_GD_GOT_HI16:
|
||||
Type = ELF::R_HEX_GD_GOT_HI16;
|
||||
break;
|
||||
case fixup_Hexagon_GD_GOT_32:
|
||||
Type = ELF::R_HEX_GD_GOT_32;
|
||||
break;
|
||||
case fixup_Hexagon_GD_GOT_16:
|
||||
Type = ELF::R_HEX_GD_GOT_16;
|
||||
break;
|
||||
case fixup_Hexagon_LD_GOT_LO16:
|
||||
Type = ELF::R_HEX_LD_GOT_LO16;
|
||||
break;
|
||||
case fixup_Hexagon_LD_GOT_HI16:
|
||||
Type = ELF::R_HEX_LD_GOT_HI16;
|
||||
break;
|
||||
case fixup_Hexagon_LD_GOT_32:
|
||||
Type = ELF::R_HEX_LD_GOT_32;
|
||||
break;
|
||||
case fixup_Hexagon_LD_GOT_16:
|
||||
Type = ELF::R_HEX_LD_GOT_16;
|
||||
break;
|
||||
case fixup_Hexagon_IE_LO16:
|
||||
Type = ELF::R_HEX_IE_LO16;
|
||||
break;
|
||||
case fixup_Hexagon_IE_HI16:
|
||||
Type = ELF::R_HEX_IE_HI16;
|
||||
break;
|
||||
case fixup_Hexagon_IE_32:
|
||||
Type = ELF::R_HEX_IE_32;
|
||||
break;
|
||||
case fixup_Hexagon_IE_GOT_LO16:
|
||||
Type = ELF::R_HEX_IE_GOT_LO16;
|
||||
break;
|
||||
case fixup_Hexagon_IE_GOT_HI16:
|
||||
Type = ELF::R_HEX_IE_GOT_HI16;
|
||||
break;
|
||||
case fixup_Hexagon_IE_GOT_32:
|
||||
Type = ELF::R_HEX_IE_GOT_32;
|
||||
break;
|
||||
case fixup_Hexagon_IE_GOT_16:
|
||||
Type = ELF::R_HEX_IE_GOT_16;
|
||||
break;
|
||||
case fixup_Hexagon_TPREL_LO16:
|
||||
Type = ELF::R_HEX_TPREL_LO16;
|
||||
break;
|
||||
case fixup_Hexagon_TPREL_HI16:
|
||||
Type = ELF::R_HEX_TPREL_HI16;
|
||||
break;
|
||||
case fixup_Hexagon_TPREL_32:
|
||||
Type = ELF::R_HEX_TPREL_32;
|
||||
break;
|
||||
case fixup_Hexagon_TPREL_16:
|
||||
Type = ELF::R_HEX_TPREL_16;
|
||||
break;
|
||||
case fixup_Hexagon_6_PCREL_X:
|
||||
Type = ELF::R_HEX_6_PCREL_X;
|
||||
break;
|
||||
case fixup_Hexagon_GOTREL_32_6_X:
|
||||
Type = ELF::R_HEX_GOTREL_32_6_X;
|
||||
break;
|
||||
case fixup_Hexagon_GOTREL_16_X:
|
||||
Type = ELF::R_HEX_GOTREL_16_X;
|
||||
break;
|
||||
case fixup_Hexagon_GOTREL_11_X:
|
||||
Type = ELF::R_HEX_GOTREL_11_X;
|
||||
break;
|
||||
case fixup_Hexagon_GOT_32_6_X:
|
||||
Type = ELF::R_HEX_GOT_32_6_X;
|
||||
break;
|
||||
case fixup_Hexagon_GOT_16_X:
|
||||
Type = ELF::R_HEX_GOT_16_X;
|
||||
break;
|
||||
case fixup_Hexagon_GOT_11_X:
|
||||
Type = ELF::R_HEX_GOT_11_X;
|
||||
break;
|
||||
case fixup_Hexagon_DTPREL_32_6_X:
|
||||
Type = ELF::R_HEX_DTPREL_32_6_X;
|
||||
break;
|
||||
case fixup_Hexagon_DTPREL_16_X:
|
||||
Type = ELF::R_HEX_DTPREL_16_X;
|
||||
break;
|
||||
case fixup_Hexagon_DTPREL_11_X:
|
||||
Type = ELF::R_HEX_DTPREL_11_X;
|
||||
break;
|
||||
case fixup_Hexagon_GD_GOT_32_6_X:
|
||||
Type = ELF::R_HEX_GD_GOT_32_6_X;
|
||||
break;
|
||||
case fixup_Hexagon_GD_GOT_16_X:
|
||||
Type = ELF::R_HEX_GD_GOT_16_X;
|
||||
break;
|
||||
case fixup_Hexagon_GD_GOT_11_X:
|
||||
Type = ELF::R_HEX_GD_GOT_11_X;
|
||||
break;
|
||||
case fixup_Hexagon_LD_GOT_32_6_X:
|
||||
Type = ELF::R_HEX_LD_GOT_32_6_X;
|
||||
break;
|
||||
case fixup_Hexagon_LD_GOT_16_X:
|
||||
Type = ELF::R_HEX_LD_GOT_16_X;
|
||||
break;
|
||||
case fixup_Hexagon_LD_GOT_11_X:
|
||||
Type = ELF::R_HEX_LD_GOT_11_X;
|
||||
break;
|
||||
case fixup_Hexagon_IE_32_6_X:
|
||||
Type = ELF::R_HEX_IE_32_6_X;
|
||||
break;
|
||||
case fixup_Hexagon_IE_16_X:
|
||||
Type = ELF::R_HEX_IE_16_X;
|
||||
break;
|
||||
case fixup_Hexagon_IE_GOT_32_6_X:
|
||||
Type = ELF::R_HEX_IE_GOT_32_6_X;
|
||||
break;
|
||||
case fixup_Hexagon_IE_GOT_16_X:
|
||||
Type = ELF::R_HEX_IE_GOT_16_X;
|
||||
break;
|
||||
case fixup_Hexagon_IE_GOT_11_X:
|
||||
Type = ELF::R_HEX_IE_GOT_11_X;
|
||||
break;
|
||||
case fixup_Hexagon_TPREL_32_6_X:
|
||||
Type = ELF::R_HEX_TPREL_32_6_X;
|
||||
break;
|
||||
case fixup_Hexagon_TPREL_16_X:
|
||||
Type = ELF::R_HEX_TPREL_16_X;
|
||||
break;
|
||||
case fixup_Hexagon_TPREL_11_X:
|
||||
Type = ELF::R_HEX_TPREL_11_X;
|
||||
break;
|
||||
switch ((unsigned)Fixup.getKind()) {
|
||||
default:
|
||||
DEBUG(dbgs() << "unrecognized relocation " << Fixup.getKind() << "\n");
|
||||
llvm_unreachable("Unimplemented Fixup kind!");
|
||||
return ELF::R_HEX_NONE;
|
||||
case FK_Data_4:
|
||||
return (IsPCRel) ? ELF::R_HEX_32_PCREL : ELF::R_HEX_32;
|
||||
case FK_PCRel_4:
|
||||
return ELF::R_HEX_32_PCREL;
|
||||
case FK_Data_2:
|
||||
return ELF::R_HEX_16;
|
||||
case FK_Data_1:
|
||||
return ELF::R_HEX_8;
|
||||
case fixup_Hexagon_B22_PCREL:
|
||||
return ELF::R_HEX_B22_PCREL;
|
||||
case fixup_Hexagon_B15_PCREL:
|
||||
return ELF::R_HEX_B15_PCREL;
|
||||
case fixup_Hexagon_B7_PCREL:
|
||||
return ELF::R_HEX_B7_PCREL;
|
||||
case fixup_Hexagon_LO16:
|
||||
return ELF::R_HEX_LO16;
|
||||
case fixup_Hexagon_HI16:
|
||||
return ELF::R_HEX_HI16;
|
||||
case fixup_Hexagon_32:
|
||||
return ELF::R_HEX_32;
|
||||
case fixup_Hexagon_16:
|
||||
return ELF::R_HEX_16;
|
||||
case fixup_Hexagon_8:
|
||||
return ELF::R_HEX_8;
|
||||
case fixup_Hexagon_GPREL16_0:
|
||||
return ELF::R_HEX_GPREL16_0;
|
||||
case fixup_Hexagon_GPREL16_1:
|
||||
return ELF::R_HEX_GPREL16_1;
|
||||
case fixup_Hexagon_GPREL16_2:
|
||||
return ELF::R_HEX_GPREL16_2;
|
||||
case fixup_Hexagon_GPREL16_3:
|
||||
return ELF::R_HEX_GPREL16_3;
|
||||
case fixup_Hexagon_HL16:
|
||||
return ELF::R_HEX_HL16;
|
||||
case fixup_Hexagon_B13_PCREL:
|
||||
return ELF::R_HEX_B13_PCREL;
|
||||
case fixup_Hexagon_B9_PCREL:
|
||||
return ELF::R_HEX_B9_PCREL;
|
||||
case fixup_Hexagon_B32_PCREL_X:
|
||||
return ELF::R_HEX_B32_PCREL_X;
|
||||
case fixup_Hexagon_32_6_X:
|
||||
return ELF::R_HEX_32_6_X;
|
||||
case fixup_Hexagon_B22_PCREL_X:
|
||||
return ELF::R_HEX_B22_PCREL_X;
|
||||
case fixup_Hexagon_B15_PCREL_X:
|
||||
return ELF::R_HEX_B15_PCREL_X;
|
||||
case fixup_Hexagon_B13_PCREL_X:
|
||||
return ELF::R_HEX_B13_PCREL_X;
|
||||
case fixup_Hexagon_B9_PCREL_X:
|
||||
return ELF::R_HEX_B9_PCREL_X;
|
||||
case fixup_Hexagon_B7_PCREL_X:
|
||||
return ELF::R_HEX_B7_PCREL_X;
|
||||
case fixup_Hexagon_16_X:
|
||||
return ELF::R_HEX_16_X;
|
||||
case fixup_Hexagon_12_X:
|
||||
return ELF::R_HEX_12_X;
|
||||
case fixup_Hexagon_11_X:
|
||||
return ELF::R_HEX_11_X;
|
||||
case fixup_Hexagon_10_X:
|
||||
return ELF::R_HEX_10_X;
|
||||
case fixup_Hexagon_9_X:
|
||||
return ELF::R_HEX_9_X;
|
||||
case fixup_Hexagon_8_X:
|
||||
return ELF::R_HEX_8_X;
|
||||
case fixup_Hexagon_7_X:
|
||||
return ELF::R_HEX_7_X;
|
||||
case fixup_Hexagon_6_X:
|
||||
return ELF::R_HEX_6_X;
|
||||
case fixup_Hexagon_32_PCREL:
|
||||
return ELF::R_HEX_32_PCREL;
|
||||
case fixup_Hexagon_COPY:
|
||||
return ELF::R_HEX_COPY;
|
||||
case fixup_Hexagon_GLOB_DAT:
|
||||
return ELF::R_HEX_GLOB_DAT;
|
||||
case fixup_Hexagon_JMP_SLOT:
|
||||
return ELF::R_HEX_JMP_SLOT;
|
||||
case fixup_Hexagon_RELATIVE:
|
||||
return ELF::R_HEX_RELATIVE;
|
||||
case fixup_Hexagon_PLT_B22_PCREL:
|
||||
return ELF::R_HEX_PLT_B22_PCREL;
|
||||
case fixup_Hexagon_GOTREL_LO16:
|
||||
return ELF::R_HEX_GOTREL_LO16;
|
||||
case fixup_Hexagon_GOTREL_HI16:
|
||||
return ELF::R_HEX_GOTREL_HI16;
|
||||
case fixup_Hexagon_GOTREL_32:
|
||||
return ELF::R_HEX_GOTREL_32;
|
||||
case fixup_Hexagon_GOT_LO16:
|
||||
return ELF::R_HEX_GOT_LO16;
|
||||
case fixup_Hexagon_GOT_HI16:
|
||||
return ELF::R_HEX_GOT_HI16;
|
||||
case fixup_Hexagon_GOT_32:
|
||||
return ELF::R_HEX_GOT_32;
|
||||
case fixup_Hexagon_GOT_16:
|
||||
return ELF::R_HEX_GOT_16;
|
||||
case fixup_Hexagon_DTPMOD_32:
|
||||
return ELF::R_HEX_DTPMOD_32;
|
||||
case fixup_Hexagon_DTPREL_LO16:
|
||||
return ELF::R_HEX_DTPREL_LO16;
|
||||
case fixup_Hexagon_DTPREL_HI16:
|
||||
return ELF::R_HEX_DTPREL_HI16;
|
||||
case fixup_Hexagon_DTPREL_32:
|
||||
return ELF::R_HEX_DTPREL_32;
|
||||
case fixup_Hexagon_DTPREL_16:
|
||||
return ELF::R_HEX_DTPREL_16;
|
||||
case fixup_Hexagon_GD_PLT_B22_PCREL:
|
||||
return ELF::R_HEX_GD_PLT_B22_PCREL;
|
||||
case fixup_Hexagon_LD_PLT_B22_PCREL:
|
||||
return ELF::R_HEX_LD_PLT_B22_PCREL;
|
||||
case fixup_Hexagon_GD_GOT_LO16:
|
||||
return ELF::R_HEX_GD_GOT_LO16;
|
||||
case fixup_Hexagon_GD_GOT_HI16:
|
||||
return ELF::R_HEX_GD_GOT_HI16;
|
||||
case fixup_Hexagon_GD_GOT_32:
|
||||
return ELF::R_HEX_GD_GOT_32;
|
||||
case fixup_Hexagon_GD_GOT_16:
|
||||
return ELF::R_HEX_GD_GOT_16;
|
||||
case fixup_Hexagon_LD_GOT_LO16:
|
||||
return ELF::R_HEX_LD_GOT_LO16;
|
||||
case fixup_Hexagon_LD_GOT_HI16:
|
||||
return ELF::R_HEX_LD_GOT_HI16;
|
||||
case fixup_Hexagon_LD_GOT_32:
|
||||
return ELF::R_HEX_LD_GOT_32;
|
||||
case fixup_Hexagon_LD_GOT_16:
|
||||
return ELF::R_HEX_LD_GOT_16;
|
||||
case fixup_Hexagon_IE_LO16:
|
||||
return ELF::R_HEX_IE_LO16;
|
||||
case fixup_Hexagon_IE_HI16:
|
||||
return ELF::R_HEX_IE_HI16;
|
||||
case fixup_Hexagon_IE_32:
|
||||
return ELF::R_HEX_IE_32;
|
||||
case fixup_Hexagon_IE_GOT_LO16:
|
||||
return ELF::R_HEX_IE_GOT_LO16;
|
||||
case fixup_Hexagon_IE_GOT_HI16:
|
||||
return ELF::R_HEX_IE_GOT_HI16;
|
||||
case fixup_Hexagon_IE_GOT_32:
|
||||
return ELF::R_HEX_IE_GOT_32;
|
||||
case fixup_Hexagon_IE_GOT_16:
|
||||
return ELF::R_HEX_IE_GOT_16;
|
||||
case fixup_Hexagon_TPREL_LO16:
|
||||
return ELF::R_HEX_TPREL_LO16;
|
||||
case fixup_Hexagon_TPREL_HI16:
|
||||
return ELF::R_HEX_TPREL_HI16;
|
||||
case fixup_Hexagon_TPREL_32:
|
||||
return ELF::R_HEX_TPREL_32;
|
||||
case fixup_Hexagon_TPREL_16:
|
||||
return ELF::R_HEX_TPREL_16;
|
||||
case fixup_Hexagon_6_PCREL_X:
|
||||
return ELF::R_HEX_6_PCREL_X;
|
||||
case fixup_Hexagon_GOTREL_32_6_X:
|
||||
return ELF::R_HEX_GOTREL_32_6_X;
|
||||
case fixup_Hexagon_GOTREL_16_X:
|
||||
return ELF::R_HEX_GOTREL_16_X;
|
||||
case fixup_Hexagon_GOTREL_11_X:
|
||||
return ELF::R_HEX_GOTREL_11_X;
|
||||
case fixup_Hexagon_GOT_32_6_X:
|
||||
return ELF::R_HEX_GOT_32_6_X;
|
||||
case fixup_Hexagon_GOT_16_X:
|
||||
return ELF::R_HEX_GOT_16_X;
|
||||
case fixup_Hexagon_GOT_11_X:
|
||||
return ELF::R_HEX_GOT_11_X;
|
||||
case fixup_Hexagon_DTPREL_32_6_X:
|
||||
return ELF::R_HEX_DTPREL_32_6_X;
|
||||
case fixup_Hexagon_DTPREL_16_X:
|
||||
return ELF::R_HEX_DTPREL_16_X;
|
||||
case fixup_Hexagon_DTPREL_11_X:
|
||||
return ELF::R_HEX_DTPREL_11_X;
|
||||
case fixup_Hexagon_GD_GOT_32_6_X:
|
||||
return ELF::R_HEX_GD_GOT_32_6_X;
|
||||
case fixup_Hexagon_GD_GOT_16_X:
|
||||
return ELF::R_HEX_GD_GOT_16_X;
|
||||
case fixup_Hexagon_GD_GOT_11_X:
|
||||
return ELF::R_HEX_GD_GOT_11_X;
|
||||
case fixup_Hexagon_LD_GOT_32_6_X:
|
||||
return ELF::R_HEX_LD_GOT_32_6_X;
|
||||
case fixup_Hexagon_LD_GOT_16_X:
|
||||
return ELF::R_HEX_LD_GOT_16_X;
|
||||
case fixup_Hexagon_LD_GOT_11_X:
|
||||
return ELF::R_HEX_LD_GOT_11_X;
|
||||
case fixup_Hexagon_IE_32_6_X:
|
||||
return ELF::R_HEX_IE_32_6_X;
|
||||
case fixup_Hexagon_IE_16_X:
|
||||
return ELF::R_HEX_IE_16_X;
|
||||
case fixup_Hexagon_IE_GOT_32_6_X:
|
||||
return ELF::R_HEX_IE_GOT_32_6_X;
|
||||
case fixup_Hexagon_IE_GOT_16_X:
|
||||
return ELF::R_HEX_IE_GOT_16_X;
|
||||
case fixup_Hexagon_IE_GOT_11_X:
|
||||
return ELF::R_HEX_IE_GOT_11_X;
|
||||
case fixup_Hexagon_TPREL_32_6_X:
|
||||
return ELF::R_HEX_TPREL_32_6_X;
|
||||
case fixup_Hexagon_TPREL_16_X:
|
||||
return ELF::R_HEX_TPREL_16_X;
|
||||
case fixup_Hexagon_TPREL_11_X:
|
||||
return ELF::R_HEX_TPREL_11_X;
|
||||
}
|
||||
return Type;
|
||||
}
|
||||
|
||||
MCObjectWriter *llvm::createHexagonELFObjectWriter(raw_pwrite_stream &OS,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,99 @@
|
|||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
|
||||
; s4_0Imm
|
||||
; CHECK: memb(r0++#-1) = r1
|
||||
define i8* @foo1(i8* %a, i8 %b) {
|
||||
store i8 %b, i8* %a
|
||||
%c = getelementptr i8, i8* %a, i32 -1
|
||||
ret i8* %c
|
||||
}
|
||||
|
||||
; s4_1Imm
|
||||
; CHECK: memh(r0++#-2) = r1
|
||||
define i16* @foo2(i16* %a, i16 %b) {
|
||||
store i16 %b, i16* %a
|
||||
%c = getelementptr i16, i16* %a, i32 -1
|
||||
ret i16* %c
|
||||
}
|
||||
|
||||
; s4_2Imm
|
||||
; CHECK: memw(r0++#-4) = r1
|
||||
define i32* @foo3(i32* %a, i32 %b) {
|
||||
store i32 %b, i32* %a
|
||||
%c = getelementptr i32, i32* %a, i32 -1
|
||||
ret i32* %c
|
||||
}
|
||||
|
||||
; s4_3Imm
|
||||
; CHECK: memd(r0++#-8) = r3:2
|
||||
define i64* @foo4(i64* %a, i64 %b) {
|
||||
store i64 %b, i64* %a
|
||||
%c = getelementptr i64, i64* %a, i32 -1
|
||||
ret i64* %c
|
||||
}
|
||||
|
||||
; s6Ext
|
||||
; CHECK: if (p0.new) memw(r0+#0)=#-1
|
||||
define void @foo5(i32* %a, i1 %b) {
|
||||
br i1 %b, label %x, label %y
|
||||
x:
|
||||
store i32 -1, i32* %a
|
||||
ret void
|
||||
y:
|
||||
ret void
|
||||
}
|
||||
|
||||
; s10Ext
|
||||
; CHECK: p0 = cmp.eq(r0, #-1)
|
||||
define i1 @foo7(i32 %a) {
|
||||
%b = icmp eq i32 %a, -1
|
||||
ret i1 %b
|
||||
}
|
||||
|
||||
; s11_0Ext
|
||||
; CHECK: memb(r0+#-1) = r1
|
||||
define void @foo8(i8* %a, i8 %b) {
|
||||
%c = getelementptr i8, i8* %a, i32 -1
|
||||
store i8 %b, i8* %c
|
||||
ret void
|
||||
}
|
||||
|
||||
; s11_1Ext
|
||||
; CHECK: memh(r0+#-2) = r1
|
||||
define void @foo9(i16* %a, i16 %b) {
|
||||
%c = getelementptr i16, i16* %a, i32 -1
|
||||
store i16 %b, i16* %c
|
||||
ret void
|
||||
}
|
||||
|
||||
; s11_2Ext
|
||||
; CHECK: memw(r0+#-4) = r1
|
||||
define void @foo10(i32* %a, i32 %b) {
|
||||
%c = getelementptr i32, i32* %a, i32 -1
|
||||
store i32 %b, i32* %c
|
||||
ret void
|
||||
}
|
||||
|
||||
; s11_3Ext
|
||||
; CHECK: memd(r0+#-8) = r3:2
|
||||
define void @foo11(i64* %a, i64 %b) {
|
||||
%c = getelementptr i64, i64* %a, i32 -1
|
||||
store i64 %b, i64* %c
|
||||
ret void
|
||||
}
|
||||
|
||||
; s12Ext
|
||||
; CHECK: if (p0.new) r0 = #-1
|
||||
define i32 @foo12(i32 %a, i1 %b) {
|
||||
br i1 %b, label %x, label %y
|
||||
x:
|
||||
ret i32 -1
|
||||
y:
|
||||
ret i32 %a
|
||||
}
|
||||
|
||||
; s16Ext
|
||||
; CHECK: r0 = #-2
|
||||
define i32 @foo13() {
|
||||
ret i32 -2
|
||||
}
|
||||
|
|
@ -49,7 +49,7 @@
|
|||
0xf1 0xff 0x5f 0x78
|
||||
# CHECK: r17 = #32767
|
||||
0xf1 0xff 0xdf 0x78
|
||||
# CHECK: r17 = ##65535
|
||||
# CHECK: r17 = #-1
|
||||
|
||||
# Transfer register
|
||||
0x11 0xc0 0x75 0x70
|
||||
|
|
|
|||
Loading…
Reference in New Issue