Adjust PPC A2 input operand latencies
On the PPC A2, instructions are only issued after their input operands are ready. Model this by specifying that input operands are read at dispatch (0 cycles after issue). This changes all input operand latencies from 1 to 0. Significant test-suite performance changes (these are 99.5% confidence intervals on 6 runs for both before and after): speedups: MultiSource/Benchmarks/sim/sim -1.21915% +/- 0.175063% MultiSource/Benchmarks/TSVC/LinearDependence-flt/LinearDependence-flt -1.23946% +/- 1.05133% SingleSource/Benchmarks/Misc/flops-2 -1.24237% +/- 0.681362% MultiSource/Applications/JM/lencod/lencod -1.33992% +/- 0.757498% MultiSource/Benchmarks/TSVC/InductionVariable-flt/InductionVariable-flt -1.51802% +/- 1.21468% MultiSource/Benchmarks/TSVC/GlobalDataFlow-flt/GlobalDataFlow-flt -2.18818% +/- 1.28605% MultiSource/Benchmarks/TSVC/Packing-flt/Packing-flt -2.21977% +/- 1.19499% SingleSource/Benchmarks/BenchmarkGame/spectral-norm -2.29822% +/- 0.671871% MultiSource/Benchmarks/TSVC/Packing-dbl/Packing-dbl -2.40975% +/- 0.355931% SingleSource/Benchmarks/Misc/fp-convert -2.41899% +/- 1.04751% MultiSource/Benchmarks/TSVC/Searching-dbl/Searching-dbl -2.50349% +/- 0.126765% SingleSource/Benchmarks/Misc/flops-3 -3.00214% +/- 0.700795% MultiSource/Benchmarks/TSVC/LoopRestructuring-flt/LoopRestructuring-flt -3.56995% +/- 3.2929% MultiSource/Applications/sgefa/sgefa -4.24908% +/- 2.00413% MultiSource/Benchmarks/ASC_Sequoia/IRSmk/IRSmk -18.1294% +/- 3.96489% regressions: MultiSource/Benchmarks/TSVC/Reductions-dbl/Reductions-dbl 1.03249% +/- 0.178547% MultiSource/Applications/hexxagon/hexxagon 1.16597% +/- 0.285235% MultiSource/Benchmarks/TSVC/IndirectAddressing-flt/IndirectAddressing-flt 1.39576% +/- 1.07855% SingleSource/Benchmarks/Misc-C++/stepanov_v1p2 1.71539% +/- 0.173182% MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1 1.90013% +/- 0.866472% MultiSource/Benchmarks/TSVC/Recurrences-dbl/Recurrences-dbl 2.39854% +/- 1.05914% MultiSource/Benchmarks/TSVC/ControlFlow-dbl/ControlFlow-dbl 2.4402% +/- 0.817904% MultiSource/Benchmarks/TSVC/LoopRestructuring-dbl/LoopRestructuring-dbl 5.87997% +/- 3.3172% MultiSource/Benchmarks/Trimaran/netbench-crc/netbench-crc 9.02643% +/- 5.79591% MultiSource/Benchmarks/VersaBench/bmm/bmm 10.3517% +/- 1.227% Obviously, there are data points on both sides of this; but I think, overall, this supports making the change. llvm-svn: 195951
This commit is contained in:
Hal Finkel
parent
7468daadda
commit
1df3205e8c
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@ -26,117 +26,117 @@ def A2_FU : FuncUnit; // FI pipeline
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def PPCA2Itineraries : ProcessorItineraries<
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[A2_XU, A2_FU], [], [
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InstrItinData<IIC_IntSimple, [InstrStage<1, [A2_XU]>],
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[1, 1, 1]>,
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[1, 0, 0]>,
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InstrItinData<IIC_IntGeneral, [InstrStage<1, [A2_XU]>],
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[2, 1, 1]>,
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[2, 0, 0]>,
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InstrItinData<IIC_IntCompare, [InstrStage<1, [A2_XU]>],
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[2, 1, 1]>,
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[2, 0, 0]>,
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InstrItinData<IIC_IntDivW, [InstrStage<1, [A2_XU]>],
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[39, 1, 1]>,
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[39, 0, 0]>,
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InstrItinData<IIC_IntDivD, [InstrStage<1, [A2_XU]>],
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[71, 1, 1]>,
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[71, 0, 0]>,
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InstrItinData<IIC_IntMulHW, [InstrStage<1, [A2_XU]>],
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[5, 1, 1]>,
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[5, 0, 0]>,
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InstrItinData<IIC_IntMulHWU, [InstrStage<1, [A2_XU]>],
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[5, 1, 1]>,
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[5, 0, 0]>,
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InstrItinData<IIC_IntMulLI, [InstrStage<1, [A2_XU]>],
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[6, 1, 1]>,
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[6, 0, 0]>,
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InstrItinData<IIC_IntRotate, [InstrStage<1, [A2_XU]>],
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[2, 1, 1]>,
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[2, 0, 0]>,
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InstrItinData<IIC_IntRotateD, [InstrStage<1, [A2_XU]>],
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[2, 1, 1]>,
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[2, 0, 0]>,
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InstrItinData<IIC_IntRotateDI, [InstrStage<1, [A2_XU]>],
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[2, 1, 1]>,
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[2, 0, 0]>,
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InstrItinData<IIC_IntShift, [InstrStage<1, [A2_XU]>],
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[2, 1, 1]>,
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[2, 0, 0]>,
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InstrItinData<IIC_IntTrapW, [InstrStage<1, [A2_XU]>],
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[2, 1]>,
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[2, 0]>,
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InstrItinData<IIC_IntTrapD, [InstrStage<1, [A2_XU]>],
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[2, 1]>,
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[2, 0]>,
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InstrItinData<IIC_BrB, [InstrStage<1, [A2_XU]>],
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[6, 1, 1]>,
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[6, 0, 0]>,
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InstrItinData<IIC_BrCR, [InstrStage<1, [A2_XU]>],
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[1, 1, 1]>,
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[1, 0, 0]>,
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InstrItinData<IIC_BrMCR, [InstrStage<1, [A2_XU]>],
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[5, 1, 1]>,
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[5, 0, 0]>,
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InstrItinData<IIC_BrMCRX, [InstrStage<1, [A2_XU]>],
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[1, 1, 1]>,
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[1, 0, 0]>,
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InstrItinData<IIC_LdStDCBA, [InstrStage<1, [A2_XU]>],
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[1, 1, 1]>,
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[1, 0, 0]>,
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InstrItinData<IIC_LdStDCBF, [InstrStage<1, [A2_XU]>],
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[1, 1, 1]>,
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[1, 0, 0]>,
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InstrItinData<IIC_LdStDCBI, [InstrStage<1, [A2_XU]>],
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[1, 1, 1]>,
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[1, 0, 0]>,
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InstrItinData<IIC_LdStLoad, [InstrStage<1, [A2_XU]>],
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[6, 1, 1]>,
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[6, 0, 0]>,
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InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [A2_XU]>],
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[6, 8, 1, 1]>,
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[6, 8, 0, 0]>,
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InstrItinData<IIC_LdStLDU, [InstrStage<1, [A2_XU]>],
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[6, 1, 1]>,
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[6, 0, 0]>,
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InstrItinData<IIC_LdStStore, [InstrStage<1, [A2_XU]>],
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[1, 1, 1]>,
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[0, 0, 0]>,
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InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [A2_XU]>],
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[2, 1, 1, 1]>,
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[2, 0, 0, 0]>,
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InstrItinData<IIC_LdStICBI, [InstrStage<1, [A2_XU]>],
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[16, 1, 1]>,
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[16, 0, 0]>,
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InstrItinData<IIC_LdStSTFD, [InstrStage<1, [A2_XU]>],
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[1, 1, 1]>,
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[0, 0, 0]>,
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InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [A2_XU]>],
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[2, 1, 1, 1]>,
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[2, 0, 0, 0]>,
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InstrItinData<IIC_LdStLFD, [InstrStage<1, [A2_XU]>],
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[7, 1, 1]>,
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[7, 0, 0]>,
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InstrItinData<IIC_LdStLFDU, [InstrStage<1, [A2_XU]>],
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[7, 9, 1, 1]>,
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[7, 9, 0, 0]>,
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InstrItinData<IIC_LdStLHA, [InstrStage<1, [A2_XU]>],
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[6, 1, 1]>,
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[6, 0, 0]>,
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InstrItinData<IIC_LdStLHAU, [InstrStage<1, [A2_XU]>],
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[6, 8, 1, 1]>,
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[6, 8, 0, 0]>,
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InstrItinData<IIC_LdStLWARX, [InstrStage<1, [A2_XU]>],
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[82, 1, 1]>, // L2 latency
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[82, 0, 0]>, // L2 latency
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InstrItinData<IIC_LdStSTD, [InstrStage<1, [A2_XU]>],
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[1, 1, 1]>,
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[0, 0, 0]>,
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InstrItinData<IIC_LdStSTDU, [InstrStage<1, [A2_XU]>],
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[2, 1, 1, 1]>,
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[2, 0, 0, 0]>,
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InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [A2_XU]>],
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[82, 1, 1]>, // L2 latency
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[82, 0, 0]>, // L2 latency
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InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [A2_XU]>],
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[82, 1, 1]>, // L2 latency
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[82, 0, 0]>, // L2 latency
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InstrItinData<IIC_LdStSync, [InstrStage<1, [A2_XU]>],
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[6]>,
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InstrItinData<IIC_SprISYNC, [InstrStage<1, [A2_XU]>],
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[16]>,
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InstrItinData<IIC_SprMTMSR, [InstrStage<1, [A2_XU]>],
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[16, 1]>,
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[16, 0]>,
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InstrItinData<IIC_SprMFCR, [InstrStage<1, [A2_XU]>],
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[6, 1]>,
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[6, 0]>,
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InstrItinData<IIC_SprMFMSR, [InstrStage<1, [A2_XU]>],
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[4, 1]>,
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[4, 0]>,
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InstrItinData<IIC_SprMFSPR, [InstrStage<1, [A2_XU]>],
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[6, 1]>,
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[6, 0]>,
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InstrItinData<IIC_SprMFTB, [InstrStage<1, [A2_XU]>],
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[4, 1]>,
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[4, 0]>,
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InstrItinData<IIC_SprMTSPR, [InstrStage<1, [A2_XU]>],
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[6, 1]>,
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[6, 0]>,
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InstrItinData<IIC_SprRFI, [InstrStage<1, [A2_XU]>],
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[16]>,
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InstrItinData<IIC_SprSC, [InstrStage<1, [A2_XU]>],
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[16]>,
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InstrItinData<IIC_FPGeneral, [InstrStage<1, [A2_FU]>],
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[6, 1, 1]>,
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[6, 0, 0]>,
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InstrItinData<IIC_FPAddSub, [InstrStage<1, [A2_FU]>],
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[6, 1, 1]>,
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[6, 0, 0]>,
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InstrItinData<IIC_FPCompare, [InstrStage<1, [A2_FU]>],
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[5, 1, 1]>,
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[5, 0, 0]>,
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InstrItinData<IIC_FPDivD, [InstrStage<1, [A2_FU]>],
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[72, 1, 1]>,
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[72, 0, 0]>,
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InstrItinData<IIC_FPDivS, [InstrStage<1, [A2_FU]>],
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[59, 1, 1]>,
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[59, 0, 0]>,
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InstrItinData<IIC_FPSqrt, [InstrStage<1, [A2_FU]>],
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[69, 1, 1]>,
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[69, 0, 0]>,
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InstrItinData<IIC_FPFused, [InstrStage<1, [A2_FU]>],
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[6, 1, 1, 1]>,
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[6, 0, 0, 0]>,
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InstrItinData<IIC_FPRes, [InstrStage<1, [A2_FU]>],
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[6, 1]>
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[6, 0]>
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]>;
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// ===---------------------------------------------------------------------===//
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