Regenerate tests to remove duplicated checks
llvm-svn: 298801
This commit is contained in:
Simon Pilgrim
parent
531a203a06
commit
1d8235a022
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@ -1133,99 +1133,52 @@ eintry:
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}
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define void @isel_crash_32b(i8* %cV_R.addr) {
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; X32-AVX2-LABEL: isel_crash_32b:
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; X32-AVX2: ## BB#0: ## %eintry
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; X32-AVX2-NEXT: pushl %ebp
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; X32-AVX2-NEXT: Lcfi1:
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; X32-AVX2-NEXT: .cfi_def_cfa_offset 8
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; X32-AVX2-NEXT: Lcfi2:
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; X32-AVX2-NEXT: .cfi_offset %ebp, -8
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; X32-AVX2-NEXT: movl %esp, %ebp
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; X32-AVX2-NEXT: Lcfi3:
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; X32-AVX2-NEXT: .cfi_def_cfa_register %ebp
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; X32-AVX2-NEXT: andl $-32, %esp
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; X32-AVX2-NEXT: subl $128, %esp
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; X32-AVX2-NEXT: movl 8(%ebp), %eax
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; X32-AVX2-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; X32-AVX2-NEXT: vmovaps %ymm0, (%esp)
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; X32-AVX2-NEXT: vpbroadcastb (%eax), %ymm1
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; X32-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
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; X32-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
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; X32-AVX2-NEXT: movl %ebp, %esp
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; X32-AVX2-NEXT: popl %ebp
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; X32-AVX2-NEXT: vzeroupper
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; X32-AVX2-NEXT: retl
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; X32-LABEL: isel_crash_32b:
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; X32: ## BB#0: ## %eintry
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; X32-NEXT: pushl %ebp
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; X32-NEXT: Lcfi1:
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; X32-NEXT: .cfi_def_cfa_offset 8
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; X32-NEXT: Lcfi2:
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; X32-NEXT: .cfi_offset %ebp, -8
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; X32-NEXT: movl %esp, %ebp
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; X32-NEXT: Lcfi3:
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; X32-NEXT: .cfi_def_cfa_register %ebp
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; X32-NEXT: andl $-32, %esp
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; X32-NEXT: subl $128, %esp
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; X32-NEXT: movl 8(%ebp), %eax
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; X32-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; X32-NEXT: vmovaps %ymm0, (%esp)
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; X32-NEXT: vpbroadcastb (%eax), %ymm1
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; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
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; X32-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
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; X32-NEXT: movl %ebp, %esp
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; X32-NEXT: popl %ebp
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; X32-NEXT: vzeroupper
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; X32-NEXT: retl
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;
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; X64-AVX2-LABEL: isel_crash_32b:
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; X64-AVX2: ## BB#0: ## %eintry
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; X64-AVX2-NEXT: pushq %rbp
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; X64-AVX2-NEXT: Lcfi0:
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; X64-AVX2-NEXT: .cfi_def_cfa_offset 16
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; X64-AVX2-NEXT: Lcfi1:
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; X64-AVX2-NEXT: .cfi_offset %rbp, -16
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; X64-AVX2-NEXT: movq %rsp, %rbp
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; X64-AVX2-NEXT: Lcfi2:
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; X64-AVX2-NEXT: .cfi_def_cfa_register %rbp
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; X64-AVX2-NEXT: andq $-32, %rsp
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; X64-AVX2-NEXT: subq $128, %rsp
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; X64-AVX2-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; X64-AVX2-NEXT: vmovaps %ymm0, (%rsp)
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; X64-AVX2-NEXT: movb (%rdi), %al
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; X64-AVX2-NEXT: vmovd %eax, %xmm1
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; X64-AVX2-NEXT: vpbroadcastb %xmm1, %ymm1
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; X64-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
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; X64-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
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; X64-AVX2-NEXT: movq %rbp, %rsp
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; X64-AVX2-NEXT: popq %rbp
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; X64-AVX2-NEXT: vzeroupper
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; X64-AVX2-NEXT: retq
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;
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; X32-AVX512VL-LABEL: isel_crash_32b:
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; X32-AVX512VL: ## BB#0: ## %eintry
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; X32-AVX512VL-NEXT: pushl %ebp
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; X32-AVX512VL-NEXT: Lcfi1:
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; X32-AVX512VL-NEXT: .cfi_def_cfa_offset 8
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; X32-AVX512VL-NEXT: Lcfi2:
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; X32-AVX512VL-NEXT: .cfi_offset %ebp, -8
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; X32-AVX512VL-NEXT: movl %esp, %ebp
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; X32-AVX512VL-NEXT: Lcfi3:
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; X32-AVX512VL-NEXT: .cfi_def_cfa_register %ebp
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; X32-AVX512VL-NEXT: andl $-32, %esp
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; X32-AVX512VL-NEXT: subl $128, %esp
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; X32-AVX512VL-NEXT: movl 8(%ebp), %eax
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; X32-AVX512VL-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; X32-AVX512VL-NEXT: vmovaps %ymm0, (%esp)
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; X32-AVX512VL-NEXT: vpbroadcastb (%eax), %ymm1
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; X32-AVX512VL-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
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; X32-AVX512VL-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
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; X32-AVX512VL-NEXT: movl %ebp, %esp
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; X32-AVX512VL-NEXT: popl %ebp
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; X32-AVX512VL-NEXT: vzeroupper
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; X32-AVX512VL-NEXT: retl
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;
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; X64-AVX512VL-LABEL: isel_crash_32b:
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; X64-AVX512VL: ## BB#0: ## %eintry
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; X64-AVX512VL-NEXT: pushq %rbp
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; X64-AVX512VL-NEXT: Lcfi0:
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; X64-AVX512VL-NEXT: .cfi_def_cfa_offset 16
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; X64-AVX512VL-NEXT: Lcfi1:
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; X64-AVX512VL-NEXT: .cfi_offset %rbp, -16
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; X64-AVX512VL-NEXT: movq %rsp, %rbp
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; X64-AVX512VL-NEXT: Lcfi2:
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; X64-AVX512VL-NEXT: .cfi_def_cfa_register %rbp
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; X64-AVX512VL-NEXT: andq $-32, %rsp
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; X64-AVX512VL-NEXT: subq $128, %rsp
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; X64-AVX512VL-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; X64-AVX512VL-NEXT: vmovaps %ymm0, (%rsp)
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; X64-AVX512VL-NEXT: movb (%rdi), %al
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; X64-AVX512VL-NEXT: vmovd %eax, %xmm1
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; X64-AVX512VL-NEXT: vpbroadcastb %xmm1, %ymm1
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; X64-AVX512VL-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
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; X64-AVX512VL-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
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; X64-AVX512VL-NEXT: movq %rbp, %rsp
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; X64-AVX512VL-NEXT: popq %rbp
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; X64-AVX512VL-NEXT: vzeroupper
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; X64-AVX512VL-NEXT: retq
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; X64-LABEL: isel_crash_32b:
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; X64: ## BB#0: ## %eintry
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; X64-NEXT: pushq %rbp
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; X64-NEXT: Lcfi0:
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; X64-NEXT: .cfi_def_cfa_offset 16
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; X64-NEXT: Lcfi1:
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; X64-NEXT: .cfi_offset %rbp, -16
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; X64-NEXT: movq %rsp, %rbp
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; X64-NEXT: Lcfi2:
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; X64-NEXT: .cfi_def_cfa_register %rbp
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; X64-NEXT: andq $-32, %rsp
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; X64-NEXT: subq $128, %rsp
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; X64-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; X64-NEXT: vmovaps %ymm0, (%rsp)
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; X64-NEXT: movb (%rdi), %al
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; X64-NEXT: vmovd %eax, %xmm1
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; X64-NEXT: vpbroadcastb %xmm1, %ymm1
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; X64-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
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; X64-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
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; X64-NEXT: movq %rbp, %rsp
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; X64-NEXT: popq %rbp
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; X64-NEXT: vzeroupper
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; X64-NEXT: retq
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eintry:
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%__a.addr.i = alloca <4 x i64>, align 16
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%__b.addr.i = alloca <4 x i64>, align 16
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@ -1282,99 +1235,52 @@ entry:
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}
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define void @isel_crash_16w(i16* %cV_R.addr) {
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; X32-AVX2-LABEL: isel_crash_16w:
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; X32-AVX2: ## BB#0: ## %eintry
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; X32-AVX2-NEXT: pushl %ebp
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; X32-AVX2-NEXT: Lcfi5:
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; X32-AVX2-NEXT: .cfi_def_cfa_offset 8
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; X32-AVX2-NEXT: Lcfi6:
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; X32-AVX2-NEXT: .cfi_offset %ebp, -8
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; X32-AVX2-NEXT: movl %esp, %ebp
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; X32-AVX2-NEXT: Lcfi7:
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; X32-AVX2-NEXT: .cfi_def_cfa_register %ebp
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; X32-AVX2-NEXT: andl $-32, %esp
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; X32-AVX2-NEXT: subl $128, %esp
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; X32-AVX2-NEXT: movl 8(%ebp), %eax
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; X32-AVX2-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; X32-AVX2-NEXT: vmovaps %ymm0, (%esp)
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; X32-AVX2-NEXT: vpbroadcastw (%eax), %ymm1
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; X32-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
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; X32-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
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; X32-AVX2-NEXT: movl %ebp, %esp
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; X32-AVX2-NEXT: popl %ebp
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; X32-AVX2-NEXT: vzeroupper
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; X32-AVX2-NEXT: retl
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; X32-LABEL: isel_crash_16w:
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; X32: ## BB#0: ## %eintry
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; X32-NEXT: pushl %ebp
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; X32-NEXT: Lcfi5:
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; X32-NEXT: .cfi_def_cfa_offset 8
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; X32-NEXT: Lcfi6:
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; X32-NEXT: .cfi_offset %ebp, -8
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; X32-NEXT: movl %esp, %ebp
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; X32-NEXT: Lcfi7:
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; X32-NEXT: .cfi_def_cfa_register %ebp
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; X32-NEXT: andl $-32, %esp
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; X32-NEXT: subl $128, %esp
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; X32-NEXT: movl 8(%ebp), %eax
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; X32-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; X32-NEXT: vmovaps %ymm0, (%esp)
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; X32-NEXT: vpbroadcastw (%eax), %ymm1
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; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
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; X32-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
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; X32-NEXT: movl %ebp, %esp
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; X32-NEXT: popl %ebp
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; X32-NEXT: vzeroupper
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; X32-NEXT: retl
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;
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; X64-AVX2-LABEL: isel_crash_16w:
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; X64-AVX2: ## BB#0: ## %eintry
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; X64-AVX2-NEXT: pushq %rbp
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; X64-AVX2-NEXT: Lcfi3:
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; X64-AVX2-NEXT: .cfi_def_cfa_offset 16
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; X64-AVX2-NEXT: Lcfi4:
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; X64-AVX2-NEXT: .cfi_offset %rbp, -16
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; X64-AVX2-NEXT: movq %rsp, %rbp
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; X64-AVX2-NEXT: Lcfi5:
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; X64-AVX2-NEXT: .cfi_def_cfa_register %rbp
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; X64-AVX2-NEXT: andq $-32, %rsp
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; X64-AVX2-NEXT: subq $128, %rsp
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; X64-AVX2-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; X64-AVX2-NEXT: vmovaps %ymm0, (%rsp)
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; X64-AVX2-NEXT: movw (%rdi), %ax
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; X64-AVX2-NEXT: vmovd %eax, %xmm1
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; X64-AVX2-NEXT: vpbroadcastw %xmm1, %ymm1
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; X64-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
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; X64-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
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; X64-AVX2-NEXT: movq %rbp, %rsp
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; X64-AVX2-NEXT: popq %rbp
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; X64-AVX2-NEXT: vzeroupper
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; X64-AVX2-NEXT: retq
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;
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; X32-AVX512VL-LABEL: isel_crash_16w:
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; X32-AVX512VL: ## BB#0: ## %eintry
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; X32-AVX512VL-NEXT: pushl %ebp
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; X32-AVX512VL-NEXT: Lcfi5:
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; X32-AVX512VL-NEXT: .cfi_def_cfa_offset 8
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; X32-AVX512VL-NEXT: Lcfi6:
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; X32-AVX512VL-NEXT: .cfi_offset %ebp, -8
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; X32-AVX512VL-NEXT: movl %esp, %ebp
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; X32-AVX512VL-NEXT: Lcfi7:
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; X32-AVX512VL-NEXT: .cfi_def_cfa_register %ebp
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; X32-AVX512VL-NEXT: andl $-32, %esp
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; X32-AVX512VL-NEXT: subl $128, %esp
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; X32-AVX512VL-NEXT: movl 8(%ebp), %eax
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; X32-AVX512VL-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; X32-AVX512VL-NEXT: vmovaps %ymm0, (%esp)
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; X32-AVX512VL-NEXT: vpbroadcastw (%eax), %ymm1
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; X32-AVX512VL-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
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; X32-AVX512VL-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
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; X32-AVX512VL-NEXT: movl %ebp, %esp
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; X32-AVX512VL-NEXT: popl %ebp
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; X32-AVX512VL-NEXT: vzeroupper
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; X32-AVX512VL-NEXT: retl
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;
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; X64-AVX512VL-LABEL: isel_crash_16w:
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; X64-AVX512VL: ## BB#0: ## %eintry
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; X64-AVX512VL-NEXT: pushq %rbp
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; X64-AVX512VL-NEXT: Lcfi3:
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; X64-AVX512VL-NEXT: .cfi_def_cfa_offset 16
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; X64-AVX512VL-NEXT: Lcfi4:
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; X64-AVX512VL-NEXT: .cfi_offset %rbp, -16
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; X64-AVX512VL-NEXT: movq %rsp, %rbp
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; X64-AVX512VL-NEXT: Lcfi5:
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; X64-AVX512VL-NEXT: .cfi_def_cfa_register %rbp
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; X64-AVX512VL-NEXT: andq $-32, %rsp
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; X64-AVX512VL-NEXT: subq $128, %rsp
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; X64-AVX512VL-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; X64-AVX512VL-NEXT: vmovaps %ymm0, (%rsp)
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; X64-AVX512VL-NEXT: movw (%rdi), %ax
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; X64-AVX512VL-NEXT: vmovd %eax, %xmm1
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; X64-AVX512VL-NEXT: vpbroadcastw %xmm1, %ymm1
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; X64-AVX512VL-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
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; X64-AVX512VL-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
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; X64-AVX512VL-NEXT: movq %rbp, %rsp
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; X64-AVX512VL-NEXT: popq %rbp
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; X64-AVX512VL-NEXT: vzeroupper
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; X64-AVX512VL-NEXT: retq
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; X64-LABEL: isel_crash_16w:
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; X64: ## BB#0: ## %eintry
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; X64-NEXT: pushq %rbp
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; X64-NEXT: Lcfi3:
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; X64-NEXT: .cfi_def_cfa_offset 16
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; X64-NEXT: Lcfi4:
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; X64-NEXT: .cfi_offset %rbp, -16
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; X64-NEXT: movq %rsp, %rbp
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; X64-NEXT: Lcfi5:
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; X64-NEXT: .cfi_def_cfa_register %rbp
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; X64-NEXT: andq $-32, %rsp
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; X64-NEXT: subq $128, %rsp
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; X64-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; X64-NEXT: vmovaps %ymm0, (%rsp)
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; X64-NEXT: movw (%rdi), %ax
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; X64-NEXT: vmovd %eax, %xmm1
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; X64-NEXT: vpbroadcastw %xmm1, %ymm1
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; X64-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
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; X64-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
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; X64-NEXT: movq %rbp, %rsp
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; X64-NEXT: popq %rbp
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; X64-NEXT: vzeroupper
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; X64-NEXT: retq
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eintry:
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%__a.addr.i = alloca <4 x i64>, align 16
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%__b.addr.i = alloca <4 x i64>, align 16
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@ -1580,34 +1486,34 @@ entry:
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}
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define void @isel_crash_4q(i64* %cV_R.addr) {
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; X32-AVX2-LABEL: isel_crash_4q:
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; X32-AVX2: ## BB#0: ## %eintry
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; X32-AVX2-NEXT: pushl %ebp
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; X32-AVX2-NEXT: Lcfi13:
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; X32-AVX2-NEXT: .cfi_def_cfa_offset 8
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; X32-AVX2-NEXT: Lcfi14:
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; X32-AVX2-NEXT: .cfi_offset %ebp, -8
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; X32-AVX2-NEXT: movl %esp, %ebp
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; X32-AVX2-NEXT: Lcfi15:
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; X32-AVX2-NEXT: .cfi_def_cfa_register %ebp
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; X32-AVX2-NEXT: andl $-32, %esp
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; X32-AVX2-NEXT: subl $128, %esp
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; X32-AVX2-NEXT: movl 8(%ebp), %eax
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; X32-AVX2-NEXT: vxorps %ymm0, %ymm0, %ymm0
|
||||
; X32-AVX2-NEXT: vmovaps %ymm0, (%esp)
|
||||
; X32-AVX2-NEXT: movl (%eax), %ecx
|
||||
; X32-AVX2-NEXT: movl 4(%eax), %eax
|
||||
; X32-AVX2-NEXT: vmovd %ecx, %xmm1
|
||||
; X32-AVX2-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
|
||||
; X32-AVX2-NEXT: vpinsrd $2, %ecx, %xmm1, %xmm1
|
||||
; X32-AVX2-NEXT: vpinsrd $3, %eax, %xmm1, %xmm1
|
||||
; X32-AVX2-NEXT: vinserti128 $1, %xmm1, %ymm1, %ymm1
|
||||
; X32-AVX2-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
|
||||
; X32-AVX2-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
|
||||
; X32-AVX2-NEXT: movl %ebp, %esp
|
||||
; X32-AVX2-NEXT: popl %ebp
|
||||
; X32-AVX2-NEXT: vzeroupper
|
||||
; X32-AVX2-NEXT: retl
|
||||
; X32-LABEL: isel_crash_4q:
|
||||
; X32: ## BB#0: ## %eintry
|
||||
; X32-NEXT: pushl %ebp
|
||||
; X32-NEXT: Lcfi13:
|
||||
; X32-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-NEXT: Lcfi14:
|
||||
; X32-NEXT: .cfi_offset %ebp, -8
|
||||
; X32-NEXT: movl %esp, %ebp
|
||||
; X32-NEXT: Lcfi15:
|
||||
; X32-NEXT: .cfi_def_cfa_register %ebp
|
||||
; X32-NEXT: andl $-32, %esp
|
||||
; X32-NEXT: subl $128, %esp
|
||||
; X32-NEXT: movl 8(%ebp), %eax
|
||||
; X32-NEXT: vxorps %ymm0, %ymm0, %ymm0
|
||||
; X32-NEXT: vmovaps %ymm0, (%esp)
|
||||
; X32-NEXT: movl (%eax), %ecx
|
||||
; X32-NEXT: movl 4(%eax), %eax
|
||||
; X32-NEXT: vmovd %ecx, %xmm1
|
||||
; X32-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
|
||||
; X32-NEXT: vpinsrd $2, %ecx, %xmm1, %xmm1
|
||||
; X32-NEXT: vpinsrd $3, %eax, %xmm1, %xmm1
|
||||
; X32-NEXT: vinserti128 $1, %xmm1, %ymm1, %ymm1
|
||||
; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
|
||||
; X32-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
|
||||
; X32-NEXT: movl %ebp, %esp
|
||||
; X32-NEXT: popl %ebp
|
||||
; X32-NEXT: vzeroupper
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; X64-AVX2-LABEL: isel_crash_4q:
|
||||
; X64-AVX2: ## BB#0: ## %eintry
|
||||
|
|
@ -1633,35 +1539,6 @@ define void @isel_crash_4q(i64* %cV_R.addr) {
|
|||
; X64-AVX2-NEXT: vzeroupper
|
||||
; X64-AVX2-NEXT: retq
|
||||
;
|
||||
; X32-AVX512VL-LABEL: isel_crash_4q:
|
||||
; X32-AVX512VL: ## BB#0: ## %eintry
|
||||
; X32-AVX512VL-NEXT: pushl %ebp
|
||||
; X32-AVX512VL-NEXT: Lcfi13:
|
||||
; X32-AVX512VL-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-AVX512VL-NEXT: Lcfi14:
|
||||
; X32-AVX512VL-NEXT: .cfi_offset %ebp, -8
|
||||
; X32-AVX512VL-NEXT: movl %esp, %ebp
|
||||
; X32-AVX512VL-NEXT: Lcfi15:
|
||||
; X32-AVX512VL-NEXT: .cfi_def_cfa_register %ebp
|
||||
; X32-AVX512VL-NEXT: andl $-32, %esp
|
||||
; X32-AVX512VL-NEXT: subl $128, %esp
|
||||
; X32-AVX512VL-NEXT: movl 8(%ebp), %eax
|
||||
; X32-AVX512VL-NEXT: vxorps %ymm0, %ymm0, %ymm0
|
||||
; X32-AVX512VL-NEXT: vmovaps %ymm0, (%esp)
|
||||
; X32-AVX512VL-NEXT: movl (%eax), %ecx
|
||||
; X32-AVX512VL-NEXT: movl 4(%eax), %eax
|
||||
; X32-AVX512VL-NEXT: vmovd %ecx, %xmm1
|
||||
; X32-AVX512VL-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
|
||||
; X32-AVX512VL-NEXT: vpinsrd $2, %ecx, %xmm1, %xmm1
|
||||
; X32-AVX512VL-NEXT: vpinsrd $3, %eax, %xmm1, %xmm1
|
||||
; X32-AVX512VL-NEXT: vinserti128 $1, %xmm1, %ymm1, %ymm1
|
||||
; X32-AVX512VL-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
|
||||
; X32-AVX512VL-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
|
||||
; X32-AVX512VL-NEXT: movl %ebp, %esp
|
||||
; X32-AVX512VL-NEXT: popl %ebp
|
||||
; X32-AVX512VL-NEXT: vzeroupper
|
||||
; X32-AVX512VL-NEXT: retl
|
||||
;
|
||||
; X64-AVX512VL-LABEL: isel_crash_4q:
|
||||
; X64-AVX512VL: ## BB#0: ## %eintry
|
||||
; X64-AVX512VL-NEXT: pushq %rbp
|
||||
|
|
|
|||
Loading…
Reference in New Issue