Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-sub
llvm-svn: 21090
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d96350095c
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1d5d767a09
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@ -25,6 +25,7 @@
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/Statistic.h"
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@ -432,6 +433,7 @@ LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
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namespace {
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namespace {
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Statistic<>NotLogic("ppc-codegen", "Number of inverted logical ops");
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Statistic<>NotLogic("ppc-codegen", "Number of inverted logical ops");
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Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations");
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//===--------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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/// ISel - PPC32 specific code to select PPC32 machine instructions for
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/// ISel - PPC32 specific code to select PPC32 machine instructions for
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/// SelectionDAG operations.
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/// SelectionDAG operations.
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@ -783,7 +785,27 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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}
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}
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case ISD::FNEG:
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case ISD::FNEG:
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if (ISD::FABS == N.getOperand(0).getOpcode()) {
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if (!NoExcessFPPrecision &&
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ISD::ADD == N.getOperand(0).getOpcode() &&
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N.getOperand(0).Val->hasOneUse() &&
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ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
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N.getOperand(0).getOperand(0).Val->hasOneUse()) {
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(1));
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Tmp3 = SelectExpr(N.getOperand(0).getOperand(1));
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Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
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BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
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} else if (!NoExcessFPPrecision &&
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ISD::SUB == N.getOperand(0).getOpcode() &&
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N.getOperand(0).Val->hasOneUse() &&
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ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
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N.getOperand(0).getOperand(0).Val->hasOneUse()) {
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(1));
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Tmp3 = SelectExpr(N.getOperand(0).getOperand(1));
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Opc = DestType == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS;
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BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
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} else if (ISD::FABS == N.getOperand(0).getOpcode()) {
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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BuildMI(BB, PPC::FNABS, 1, Result).addReg(Tmp1);
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BuildMI(BB, PPC::FNABS, 1, Result).addReg(Tmp1);
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} else {
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} else {
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@ -826,14 +848,44 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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return Result;
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return Result;
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}
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}
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case ISD::MUL:
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case ISD::ADD:
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case ISD::ADD:
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if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
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N.getOperand(0).Val->hasOneUse()) {
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++FusedFP; // Statistic
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
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Tmp3 = SelectExpr(N.getOperand(1));
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Opc = DestType == MVT::f64 ? PPC::FMADD : PPC::FMADDS;
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BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
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return Result;
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}
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Opc = DestType == MVT::f64 ? PPC::FADD : PPC::FADDS;
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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case ISD::SUB:
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case ISD::SUB:
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if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
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N.getOperand(0).Val->hasOneUse()) {
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++FusedFP; // Statistic
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
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Tmp3 = SelectExpr(N.getOperand(1));
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Opc = DestType == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS;
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BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
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return Result;
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}
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Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS;
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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case ISD::MUL:
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case ISD::SDIV:
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case ISD::SDIV:
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switch( opcode ) {
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switch( opcode ) {
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case ISD::MUL: Opc = DestType == MVT::f64 ? PPC::FMUL : PPC::FMULS; break;
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case ISD::MUL: Opc = DestType == MVT::f64 ? PPC::FMUL : PPC::FMULS; break;
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case ISD::ADD: Opc = DestType == MVT::f64 ? PPC::FADD : PPC::FADDS; break;
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case ISD::SUB: Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS; break;
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case ISD::SDIV: Opc = DestType == MVT::f64 ? PPC::FDIV : PPC::FDIVS; break;
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case ISD::SDIV: Opc = DestType == MVT::f64 ? PPC::FDIV : PPC::FDIVS; break;
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};
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};
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp1 = SelectExpr(N.getOperand(0));
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