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(X & Y) & C == 0 if either X&C or Y&C are zero 

llvm-svn: 23678
This commit is contained in:
Chris Lattner 2005-10-09 22:12:36 +00:00
parent 03b9eb506c
commit 1d3dc00674
2 changed files with 12 additions and 3 deletions
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7
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -176,10 +176,15 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
case ISD::AND:
// If either of the operands has zero bits, the result will too.
if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) ||
MaskedValueIsZero(Op.getOperand(0), Mask, TLI))
return true;
// (X & C1) & C2 == 0 iff C1 & C2 == 0.
if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
// FALL THROUGH
return false;
case ISD::OR:
case ISD::XOR:
return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&

8
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -608,11 +608,15 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
case ISD::AND:
// If either of the operands has zero bits, the result will too.
if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) ||
MaskedValueIsZero(Op.getOperand(0), Mask, TLI))
return true;
// (X & C1) & C2 == 0 iff C1 & C2 == 0.
if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
// FALL THROUGH
return false;
case ISD::OR:
case ISD::XOR:
return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&