Update MachineVerifier to check the new physreg live-in rules.
llvm-svn: 150496
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@ -75,6 +75,7 @@ namespace {
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const MachineInstr *FirstTerminator;
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BitVector regsReserved;
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BitVector regsAllocatable;
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RegSet regsLive;
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RegVector regsDefined, regsDead, regsKilled;
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RegSet regsLiveInButUnused;
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@ -175,6 +176,10 @@ namespace {
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return Reg < regsReserved.size() && regsReserved.test(Reg);
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}
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bool isAllocatable(unsigned Reg) {
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return Reg < regsAllocatable.size() && regsAllocatable.test(Reg);
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}
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// Analysis information if available
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LiveVariables *LiveVars;
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LiveIntervals *LiveInts;
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@ -380,6 +385,9 @@ void MachineVerifier::visitMachineFunctionBefore() {
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regsReserved.set(*Sub);
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}
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}
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regsAllocatable = TRI->getAllocatableSet(*MF);
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markReachable(&MF->front());
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}
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@ -397,6 +405,20 @@ void
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MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
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FirstTerminator = 0;
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if (MRI->isSSA()) {
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// If this block has allocatable physical registers live-in, check that
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// it is an entry block or landing pad.
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for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
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LE = MBB->livein_end();
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LI != LE; ++LI) {
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unsigned reg = *LI;
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if (isAllocatable(reg) && !MBB->isLandingPad() &&
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MBB != MBB->getParent()->begin()) {
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report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
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}
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}
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}
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// Count the number of landing pad successors.
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SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
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for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
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