diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 35c9056d536b..8084cd58e9e9 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -7078,7 +7078,7 @@ bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
     if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
       return false;
     // If BaseGV requires a register, we cannot also have a BaseReg.
-    if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine(), false) &&
+    if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine()) &&
         AM.HasBaseReg)
       return false;
 
@@ -8841,8 +8841,8 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
     }
     // If we require an extra load to get this address, as in PIC mode, we
     // can't accept it.
-    if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(),
-                                       getTargetMachine(), false))
+    if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
+                                       false))
       return;
 
     if (hasMemory)
diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp
index f181b38cb289..7d1f972b4e7f 100644
--- a/llvm/lib/Target/X86/X86Subtarget.cpp
+++ b/llvm/lib/Target/X86/X86Subtarget.cpp
@@ -76,15 +76,14 @@ bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue* GV,
 /// cases where GVRequiresExtraLoad is true.  Some variations of PIC require
 /// a register, but not an extra load.
 bool X86Subtarget::GVRequiresRegister(const GlobalValue *GV,
-                                      const TargetMachine& TM,
-                                      bool isDirectCall) const {
-  if (GVRequiresExtraLoad(GV, TM, isDirectCall))
+                                      const TargetMachine &TM) const {
+  if (GVRequiresExtraLoad(GV, TM, false))
     return true;
+  
   // Code below here need only consider cases where GVRequiresExtraLoad
   // returns false.
   if (TM.getRelocationModel() == Reloc::PIC_)
-    return !isDirectCall && 
-      (GV->hasLocalLinkage() || GV->hasExternalLinkage());
+    return GV->hasLocalLinkage() || GV->hasExternalLinkage();
   return false;
 }
 
diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h
index 5a4f8c5e27e6..db3b5d5eaf9b 100644
--- a/llvm/lib/Target/X86/X86Subtarget.h
+++ b/llvm/lib/Target/X86/X86Subtarget.h
@@ -201,14 +201,13 @@ public:
   /// symbols are indirect, loading the value at address GV rather then the
   /// value of GV itself. This means that the GlobalAddress must be in the base
   /// or index register of the address, not the GV offset field.
-  bool GVRequiresExtraLoad(const GlobalValue* GV, const TargetMachine& TM,
+  bool GVRequiresExtraLoad(const GlobalValue* GV, const TargetMachine &TM,
                            bool isDirectCall) const;
 
   /// True if accessing the GV requires a register.  This is a superset of the
   /// cases where GVRequiresExtraLoad is true.  Some variations of PIC require
   /// a register, but not an extra load.
-  bool GVRequiresRegister(const GlobalValue* GV, const TargetMachine& TM,
-                           bool isDirectCall) const;
+  bool GVRequiresRegister(const GlobalValue* GV, const TargetMachine &TM) const;
 
   /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
   /// to immediate address.