parent
a4d29b8e20
commit
1ca049959f
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@ -124,7 +124,7 @@ static bool isAddConstantOp(const MachineInstr &MI, int64_t &Amount) {
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switch (MI.getOpcode()) {
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switch (MI.getOpcode()) {
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case ARC::SUB_rru6:
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case ARC::SUB_rru6:
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Sign = -1;
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Sign = -1;
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// LLVM_FALLTHROUGH
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LLVM_FALLTHROUGH;
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case ARC::ADD_rru6:
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case ARC::ADD_rru6:
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assert(MI.getOperand(2).isImm() && "Expected immediate operand");
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assert(MI.getOperand(2).isImm() && "Expected immediate operand");
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Amount = Sign * MI.getOperand(2).getImm();
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Amount = Sign * MI.getOperand(2).getImm();
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