[LLDB][MIPS] Emulate instruction using MCDisassembler
Patch by Jaydeep Patil EmulateInstructionMIPS64 has been modified to use llvm::MCDisassembler instead of duplicating the decoding logic. Added emulation of few branch instructions for software single stepping Reviewers: clayborg, jasonmolenda Subscribers: bhushan, mohit.bhakkad, sagar, lldb-commits. Differential Revision: http://reviews.llvm.org/D9319 llvm-svn: 236411
This commit is contained in:
Mohit K. Bhakkad
parent
f9900379b4
commit
1c34f7cf18
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@ -11,15 +11,26 @@
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#include <stdlib.h>
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#include "lldb/Core/ArchSpec.h"
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#include "llvm-c/Disassembler.h"
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#include "llvm/Support/TargetSelect.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "lldb/Core/Address.h"
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#include "lldb/Core/Opcode.h"
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#include "lldb/Core/ArchSpec.h"
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#include "lldb/Core/ConstString.h"
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#include "lldb/Core/PluginManager.h"
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#include "lldb/Core/DataExtractor.h"
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#include "lldb/Core/Stream.h"
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#include "lldb/Symbol/UnwindPlan.h"
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#include "llvm/ADT/STLExtras.h"
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//#include "llvm/Support/MathExtras.h" // for SignExtend32 template function
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#include "Plugins/Process/Utility/InstructionUtils.h"
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#include "Plugins/Process/Utility/RegisterContext_mips64.h"
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@ -37,6 +48,32 @@ using namespace lldb_private;
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//
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//----------------------------------------------------------------------
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EmulateInstructionMIPS64::EmulateInstructionMIPS64 (const lldb_private::ArchSpec &arch) :
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EmulateInstruction (arch)
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{
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/* Create instance of llvm::MCDisassembler */
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std::string Error;
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llvm::Triple triple = arch.GetTriple();
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const llvm::Target *target = llvm::TargetRegistry::lookupTarget (triple.getTriple(), Error);
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assert (target);
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m_reg_info.reset (target->createMCRegInfo (triple.getTriple()));
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assert (m_reg_info.get());
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m_insn_info.reset (target->createMCInstrInfo());
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assert (m_insn_info.get());
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m_asm_info.reset (target->createMCAsmInfo (*m_reg_info, triple.getTriple()));
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m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), "", ""));
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assert (m_asm_info.get() && m_subtype_info.get());
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m_context.reset (new llvm::MCContext (m_asm_info.get(), m_reg_info.get(), nullptr));
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assert (m_context.get());
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m_disasm.reset (target->createMCDisassembler (*m_subtype_info, *m_context));
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assert (m_disasm.get());
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}
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void
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EmulateInstructionMIPS64::Initialize ()
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{
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@ -171,8 +208,8 @@ EmulateInstructionMIPS64::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_n
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case LLDB_REGNUM_GENERIC_RA: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_ra_mips64; break;
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case LLDB_REGNUM_GENERIC_FLAGS: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_sr_mips64; break;
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return true;
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default: return false;
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default:
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return false;
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}
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}
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@ -187,7 +224,7 @@ EmulateInstructionMIPS64::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_n
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reg_info.format = eFormatHex;
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reg_info.encoding = eEncodingUint;
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}
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else if (reg_num >= gcc_dwarf_zero_mips64 && reg_num <= gcc_dwarf_pc_mips64)
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else if ((int)reg_num >= gcc_dwarf_zero_mips64 && (int)reg_num <= gcc_dwarf_pc_mips64)
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{
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reg_info.byte_size = 8;
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reg_info.format = eFormatHex;
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@ -216,33 +253,35 @@ EmulateInstructionMIPS64::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_n
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return false;
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}
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EmulateInstructionMIPS64::Opcode*
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EmulateInstructionMIPS64::GetOpcodeForInstruction (const uint32_t opcode)
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EmulateInstructionMIPS64::MipsOpcode*
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EmulateInstructionMIPS64::GetOpcodeForInstruction (const char *op_name)
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{
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static EmulateInstructionMIPS64::Opcode
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static EmulateInstructionMIPS64::MipsOpcode
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g_opcodes[] =
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{
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//----------------------------------------------------------------------
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// Prologue/Epilogue instructions
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//----------------------------------------------------------------------
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{ "DADDiu", &EmulateInstructionMIPS64::Emulate_DADDiu, "DADDIU rt,rs,immediate" },
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{ "SD", &EmulateInstructionMIPS64::Emulate_SD, "SD rt,offset(rs)" },
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{ "LD", &EmulateInstructionMIPS64::Emulate_LD, "LD rt,offset(base)" },
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// stack adjustment
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{ 0xffff0000, 0x67bd0000, &EmulateInstructionMIPS64::Emulate_addsp_imm, "DADDIU rt, rs, immediate" },
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// store register
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{ 0xfc000000, 0xfc000000, &EmulateInstructionMIPS64::Emulate_store, "SD rt, offset(Rn)" },
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// Load register
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{ 0xfc000000, 0xdc000000, &EmulateInstructionMIPS64::Emulate_load, "LD rt, offset(base)" },
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//----------------------------------------------------------------------
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// Branch instructions
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//----------------------------------------------------------------------
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{ "B", &EmulateInstructionMIPS64::Emulate_B, "B offset" },
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{ "BAL", &EmulateInstructionMIPS64::Emulate_BAL, "BAL offset" },
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{ "BALC", &EmulateInstructionMIPS64::Emulate_BALC, "BALC offset" },
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};
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static const size_t k_num_mips_opcodes = llvm::array_lengthof(g_opcodes);
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for (size_t i=0; i<k_num_mips_opcodes; ++i)
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for (size_t i = 0; i < k_num_mips_opcodes; ++i)
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{
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if ((g_opcodes[i].mask & opcode) == g_opcodes[i].value)
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if (! strcasecmp (g_opcodes[i].op_name, op_name))
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return &g_opcodes[i];
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}
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return NULL;
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}
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@ -266,22 +305,70 @@ EmulateInstructionMIPS64::ReadInstruction ()
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bool
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EmulateInstructionMIPS64::EvaluateInstruction (uint32_t evaluate_options)
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{
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uint32_t opcode = m_opcode.GetOpcode32();
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if (GetByteOrder() == eByteOrderBig)
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opcode = llvm::ByteSwap_32(opcode);
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Opcode *opcode_data = GetOpcodeForInstruction(opcode);
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bool success = false;
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llvm::MCInst mc_insn;
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uint64_t insn_size;
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DataExtractor data;
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/* Keep the complexity of the decode logic with the llvm::MCDisassembler class. */
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if (m_opcode.GetData (data))
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{
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llvm::MCDisassembler::DecodeStatus decode_status;
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llvm::ArrayRef<uint8_t> raw_insn (data.GetDataStart(), data.GetByteSize());
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decode_status = m_disasm->getInstruction (mc_insn, insn_size, raw_insn, m_addr, llvm::nulls(), llvm::nulls());
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if (decode_status != llvm::MCDisassembler::Success)
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return false;
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}
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/*
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* mc_insn.getOpcode() returns decoded opcode. However to make use
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* of llvm::Mips::<insn> we would need "MipsGenInstrInfo.inc".
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*/
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const char *op_name = m_insn_info->getName (mc_insn.getOpcode ());
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if (op_name == NULL)
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return false;
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/*
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* Decoding has been done already. Just get the call-back function
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* and emulate the instruction.
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*/
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MipsOpcode *opcode_data = GetOpcodeForInstruction (op_name);
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if (opcode_data == NULL)
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return false;
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// Call the Emulate... function.
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success = (this->*opcode_data->callback) (opcode);
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uint64_t old_pc = 0, new_pc = 0;
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const bool auto_advance_pc = evaluate_options & eEmulateInstructionOptionAutoAdvancePC;
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if (auto_advance_pc)
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{
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old_pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
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if (!success)
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return false;
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}
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/* emulate instruction */
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success = (this->*opcode_data->callback) (mc_insn);
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if (!success)
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return false;
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if (auto_advance_pc)
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{
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new_pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
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if (!success)
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return false;
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/* If we haven't changed the PC, change it here */
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if (old_pc == new_pc)
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{
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new_pc += 4;
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Context context;
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if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, new_pc))
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return false;
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}
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}
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return true;
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}
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@ -303,7 +390,6 @@ EmulateInstructionMIPS64::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan)
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unwind_plan.AppendRow (row);
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// All other registers are the same.
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unwind_plan.SetSourceName ("EmulateInstructionMIPS64");
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unwind_plan.SetSourcedFromCompiler (eLazyBoolNo);
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unwind_plan.SetUnwindPlanValidAtAllInstructions (eLazyBoolYes);
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@ -324,6 +410,7 @@ EmulateInstructionMIPS64::nonvolatile_reg_p (uint64_t regnum)
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case gcc_dwarf_r21_mips64:
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case gcc_dwarf_r22_mips64:
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case gcc_dwarf_r23_mips64:
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case gcc_dwarf_gp_mips64:
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case gcc_dwarf_sp_mips64:
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case gcc_dwarf_r30_mips64:
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case gcc_dwarf_ra_mips64:
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@ -335,111 +422,209 @@ EmulateInstructionMIPS64::nonvolatile_reg_p (uint64_t regnum)
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}
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bool
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EmulateInstructionMIPS64::Emulate_addsp_imm (const uint32_t opcode)
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EmulateInstructionMIPS64::Emulate_DADDiu (llvm::MCInst& insn)
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{
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/* Get immediate operand */
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const uint32_t imm16 = Bits32(opcode, 15, 0);
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bool success = false;
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uint64_t result;
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const uint32_t imm16 = insn.getOperand(2).getImm();
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uint64_t imm = SignedBits(imm16, 15, 0);
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uint64_t result;
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uint32_t src, dst;
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uint64_t operand1 = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_sp_mips64, 0, &success);
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uint64_t operand2 = imm;
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dst = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
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src = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
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result = operand1 + operand2;
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Context context;
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RegisterInfo reg_info_Rn;
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if (GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_sp_mips64, reg_info_Rn))
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context.SetRegisterPlusOffset (reg_info_Rn, imm);
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/* Check if this is daddiu sp,<src>,imm16 */
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if (dst == gcc_dwarf_sp_mips64)
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{
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/* read <src> register */
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uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + src, 0, &success);
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if (!success)
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return false;
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/* We are allocating bytes on stack */
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context.type = eContextAdjustStackPointer;
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result = src_opd_val + imm;
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WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_sp_mips64, result);
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Context context;
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RegisterInfo reg_info_sp;
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if (GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_sp_mips64, reg_info_sp))
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context.SetRegisterPlusOffset (reg_info_sp, imm);
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/* We are allocating bytes on stack */
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context.type = eContextAdjustStackPointer;
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WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_sp_mips64, result);
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}
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return true;
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}
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bool
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EmulateInstructionMIPS64::Emulate_store (const uint32_t opcode)
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EmulateInstructionMIPS64::Emulate_SD (llvm::MCInst& insn)
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{
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uint32_t imm16 = Bits32(opcode, 15, 0);
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uint32_t Rt = Bits32(opcode, 20, 16);
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uint32_t base = Bits32(opcode, 25, 21);
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uint64_t imm = SignedBits(imm16, 15, 0);
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uint64_t address;
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integer n = UInt(base);
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integer t = UInt(Rt);
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RegisterValue data_Rt;
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RegisterInfo reg_info_base;
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RegisterInfo reg_info_Rt;
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if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + n, reg_info_base))
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return false;
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if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + t, reg_info_Rt))
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return false;
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bool success = false;
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Context context_t;
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uint32_t imm16 = insn.getOperand(2).getImm();
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uint64_t imm = SignedBits(imm16, 15, 0);
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uint32_t src, base;
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src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
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base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
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/* We look for sp based non-volatile register stores */
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if (n == 29 && nonvolatile_reg_p(t))
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address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_sp_mips64, 0, &success);
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else
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if (base == gcc_dwarf_sp_mips64 && nonvolatile_reg_p (src))
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{
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uint64_t address;
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RegisterInfo reg_info_base;
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RegisterInfo reg_info_src;
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if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, reg_info_base)
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|| !GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + src, reg_info_src))
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return false;
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/* read SP */
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address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, 0, &success);
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if (!success)
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return false;
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/* destination address */
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address = address + imm;
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Context context;
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RegisterValue data_src;
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context.type = eContextPushRegisterOnStack;
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context.SetRegisterToRegisterPlusOffset (reg_info_src, reg_info_base, 0);
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uint8_t buffer [RegisterValue::kMaxRegisterByteSize];
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Error error;
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if (!ReadRegister (®_info_base, data_src))
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return false;
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if (data_src.GetAsMemoryData (®_info_src, buffer, reg_info_src.byte_size, eByteOrderLittle, error) == 0)
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return false;
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if (!WriteMemory (context, address, buffer, reg_info_src.byte_size))
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return false;
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return true;
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}
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return false;
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}
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bool
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EmulateInstructionMIPS64::Emulate_LD (llvm::MCInst& insn)
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{
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uint32_t src, base;
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src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
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base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
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if (base == gcc_dwarf_sp_mips64 && nonvolatile_reg_p (src))
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{
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RegisterValue data_src;
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RegisterInfo reg_info_src;
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if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + src, reg_info_src))
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return false;
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Context context;
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context.type = eContextRegisterLoad;
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if (!WriteRegister (context, ®_info_src, data_src))
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return false;
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return true;
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}
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return false;
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}
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bool
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EmulateInstructionMIPS64::Emulate_B (llvm::MCInst& insn)
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{
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bool success = false;
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uint64_t offset, pc, target;
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/*
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* B offset
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* PC = PC + sign_ext (offset << 2)
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*/
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offset = insn.getOperand(0).getImm() << 2;
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offset = SignedBits (offset, 17, 0);
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pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
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if (!success)
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return false;
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/* Calculate address to store */
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address = address + imm;
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target = pc + offset;
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context_t.type = eContextPushRegisterOnStack;
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context_t.SetRegisterToRegisterPlusOffset (reg_info_Rt, reg_info_base, 0);
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Context context;
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context.type = eContextRelativeBranchImmediate;
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uint8_t buffer [RegisterValue::kMaxRegisterByteSize];
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Error error;
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if (!ReadRegister (®_info_Rt, data_Rt))
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return false;
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if (data_Rt.GetAsMemoryData(®_info_Rt, buffer, reg_info_Rt.byte_size, eByteOrderLittle, error) == 0)
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return false;
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if (!WriteMemory(context_t, address, buffer, reg_info_Rt.byte_size))
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if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
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return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool
|
||||
EmulateInstructionMIPS64::Emulate_load (const uint32_t opcode)
|
||||
EmulateInstructionMIPS64::Emulate_BAL (llvm::MCInst& insn)
|
||||
{
|
||||
uint32_t Rt = Bits32(opcode, 20, 16);
|
||||
uint32_t base = Bits32(opcode, 25, 21);
|
||||
bool success = false;
|
||||
uint64_t offset, pc, target;
|
||||
|
||||
integer n = UInt(base);
|
||||
integer t = UInt(Rt);
|
||||
|
||||
RegisterValue data_Rt;
|
||||
RegisterInfo reg_info_Rt;
|
||||
/*
|
||||
* BAL offset
|
||||
* offset = sign_ext (offset << 2)
|
||||
* RA = PC + 8
|
||||
* PC = PC + offset
|
||||
*/
|
||||
offset = insn.getOperand(0).getImm() << 2;
|
||||
offset = SignedBits (offset, 17, 0);
|
||||
|
||||
if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + t, reg_info_Rt))
|
||||
pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
|
||||
if (!success)
|
||||
return false;
|
||||
|
||||
Context context_t;
|
||||
target = pc + offset;
|
||||
|
||||
/* We are looking for "saved register" being restored from stack */
|
||||
if (!(n == 29) || !nonvolatile_reg_p(t))
|
||||
Context context;
|
||||
|
||||
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
|
||||
return false;
|
||||
|
||||
context_t.type = eContextRegisterLoad;
|
||||
|
||||
if (!WriteRegister (context_t, ®_info_Rt, data_Rt))
|
||||
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 8))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool
|
||||
EmulateInstructionMIPS64::Emulate_BALC (llvm::MCInst& insn)
|
||||
{
|
||||
bool success = false;
|
||||
uint64_t offset, pc, target;
|
||||
|
||||
/*
|
||||
* BALC offset
|
||||
* offset = sign_ext (offset << 2)
|
||||
* RA = PC + 4
|
||||
* PC = PC + 4 + offset
|
||||
*/
|
||||
offset = insn.getOperand(0).getImm() << 2;
|
||||
offset = SignedBits (offset, 17, 0);
|
||||
|
||||
pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
|
||||
if (!success)
|
||||
return false;
|
||||
|
||||
target = pc + 4 + offset;
|
||||
|
||||
Context context;
|
||||
|
||||
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
|
||||
return false;
|
||||
|
||||
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
|
|
|
|||
|
|
@ -10,6 +10,17 @@
|
|||
#ifndef EmulateInstructionMIPS64_h_
|
||||
#define EmulateInstructionMIPS64_h_
|
||||
|
||||
namespace llvm
|
||||
{
|
||||
class MCDisassembler;
|
||||
class MCSubtargetInfo;
|
||||
class MCRegisterInfo;
|
||||
class MCAsmInfo;
|
||||
class MCContext;
|
||||
class MCInstrInfo;
|
||||
class MCInst;
|
||||
}
|
||||
|
||||
#include "lldb/Core/EmulateInstruction.h"
|
||||
#include "lldb/Core/Error.h"
|
||||
#include "lldb/Interpreter/OptionValue.h"
|
||||
|
|
@ -67,10 +78,7 @@ public:
|
|||
bool
|
||||
SetTargetTriple (const lldb_private::ArchSpec &arch);
|
||||
|
||||
EmulateInstructionMIPS64 (const lldb_private::ArchSpec &arch) :
|
||||
EmulateInstruction (arch)
|
||||
{
|
||||
}
|
||||
EmulateInstructionMIPS64 (const lldb_private::ArchSpec &arch);
|
||||
|
||||
virtual bool
|
||||
SupportsEmulatingInstructionsOfType (lldb_private::InstructionType inst_type)
|
||||
|
|
@ -105,23 +113,31 @@ protected:
|
|||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t mask;
|
||||
uint32_t value;
|
||||
bool (EmulateInstructionMIPS64::*callback) (const uint32_t opcode);
|
||||
const char *name;
|
||||
} Opcode;
|
||||
const char *op_name;
|
||||
bool (EmulateInstructionMIPS64::*callback) (llvm::MCInst& insn);
|
||||
const char *insn_name;
|
||||
} MipsOpcode;
|
||||
|
||||
static Opcode*
|
||||
GetOpcodeForInstruction (const uint32_t opcode);
|
||||
static MipsOpcode*
|
||||
GetOpcodeForInstruction (const char *op_name);
|
||||
|
||||
bool
|
||||
Emulate_addsp_imm (const uint32_t opcode);
|
||||
|
||||
bool
|
||||
Emulate_store (const uint32_t opcode);
|
||||
Emulate_DADDiu (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_load (const uint32_t opcode);
|
||||
Emulate_SD (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_LD (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_B (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BAL (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BALC (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
nonvolatile_reg_p (uint64_t regnum);
|
||||
|
|
@ -129,6 +145,13 @@ protected:
|
|||
const char *
|
||||
GetRegisterName (unsigned reg_num, bool altnernate_name);
|
||||
|
||||
private:
|
||||
std::unique_ptr<llvm::MCDisassembler> m_disasm;
|
||||
std::unique_ptr<llvm::MCSubtargetInfo> m_subtype_info;
|
||||
std::unique_ptr<llvm::MCRegisterInfo> m_reg_info;
|
||||
std::unique_ptr<llvm::MCAsmInfo> m_asm_info;
|
||||
std::unique_ptr<llvm::MCContext> m_context;
|
||||
std::unique_ptr<llvm::MCInstrInfo> m_insn_info;
|
||||
};
|
||||
|
||||
#endif // EmulateInstructionMIPS64_h_
|
||||
|
|
|
|||
Loading…
Reference in New Issue