[CodeGen] Check for HardwareLoop Latch ExitBlock
The HardwareLoops pass finds exit blocks with a scevable exit count. If the target specifies to update the loop counter in a register, through a phi, we need to ensure that the exit block is a latch so that we can insert the phi with the correct value for the incoming edge. Differential Revision: https://reviews.llvm.org/D63336 llvm-svn: 363556
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Sam Parker
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@ -448,9 +448,7 @@ public:
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void getUnrollingPreferences(Loop *L, ScalarEvolution &,
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UnrollingPreferences &UP) const;
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/// Attributes of a target dependent hardware loop. Here, the term 'element'
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/// describes the work performed by an IR loop that has not been vectorized
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/// by the compiler.
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/// Attributes of a target dependent hardware loop.
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struct HardwareLoopInfo {
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HardwareLoopInfo() = delete;
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HardwareLoopInfo(Loop *L) : L(L) { }
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@ -459,10 +457,10 @@ public:
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BranchInst *ExitBranch = nullptr;
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const SCEV *ExitCount = nullptr;
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IntegerType *CountType = nullptr;
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Value *LoopDecrement = nullptr; // The maximum number of elements
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// processed in the loop body.
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Value *LoopDecrement = nullptr; // Decrement the loop counter by this
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// value in every iteration.
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bool IsNestingLegal = false; // Can a hardware loop be a parent to
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// another hardware loop.
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// another hardware loop?
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bool CounterInReg = false; // Should loop counter be updated in
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// the loop via a phi?
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};
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@ -235,7 +235,17 @@ bool HardwareLoops::TryConvertLoop(TTI::HardwareLoopInfo &HWLoopInfo) {
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for (SmallVectorImpl<BasicBlock *>::iterator I = ExitingBlocks.begin(),
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IE = ExitingBlocks.end(); I != IE; ++I) {
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const SCEV *EC = SE->getExitCount(L, *I);
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BasicBlock *BB = *I;
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// If we pass the updated counter back through a phi, we need to know
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// which latch the updated value will be coming from.
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if (!L->isLoopLatch(BB)) {
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if ((ForceHardwareLoopPHI.getNumOccurrences() && ForceHardwareLoopPHI) ||
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HWLoopInfo.CounterInReg)
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continue;
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}
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const SCEV *EC = SE->getExitCount(L, BB);
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if (isa<SCEVCouldNotCompute>(EC))
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continue;
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if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
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@ -251,7 +261,7 @@ bool HardwareLoops::TryConvertLoop(TTI::HardwareLoopInfo &HWLoopInfo) {
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// If this exiting block is contained in a nested loop, it is not eligible
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// for insertion of the branch-and-decrement since the inner loop would
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// end up messing up the value in the CTR.
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if (!HWLoopInfo.IsNestingLegal && LI->getLoopFor(*I) != L &&
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if (!HWLoopInfo.IsNestingLegal && LI->getLoopFor(BB) != L &&
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!ForceNestedLoop)
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continue;
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@ -278,7 +288,7 @@ bool HardwareLoops::TryConvertLoop(TTI::HardwareLoopInfo &HWLoopInfo) {
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continue;
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// Make sure this blocks ends with a conditional branch.
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Instruction *TI = (*I)->getTerminator();
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Instruction *TI = BB->getTerminator();
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if (!TI)
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continue;
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@ -702,10 +702,6 @@ bool ARMTTIImpl::isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
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if (!ST->hasLOB() || DisableLowOverheadLoops)
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return false;
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// For now, for simplicity, only support loops with one exit block.
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if (!L->getExitBlock())
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return false;
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if (!SE.hasLoopInvariantBackedgeTakenCount(L))
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return false;
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@ -135,6 +135,82 @@ while.end7:
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ret void
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}
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; CHECK-LABEL: not_rotated
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; CHECK-NOT: call void @llvm.set.loop.iterations
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; CHECK-NOT: call i32 @llvm.loop.decrement.i32
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define void @not_rotated(i32, i16* nocapture, i16 signext) {
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br label %4
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4:
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%5 = phi i32 [ 0, %3 ], [ %19, %18 ]
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%6 = icmp eq i32 %5, %0
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br i1 %6, label %20, label %7
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7:
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%8 = mul i32 %5, %0
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br label %9
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9:
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%10 = phi i32 [ %17, %12 ], [ 0, %7 ]
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%11 = icmp eq i32 %10, %0
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br i1 %11, label %18, label %12
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12:
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%13 = add i32 %10, %8
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%14 = getelementptr inbounds i16, i16* %1, i32 %13
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%15 = load i16, i16* %14, align 2
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%16 = add i16 %15, %2
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store i16 %16, i16* %14, align 2
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%17 = add i32 %10, 1
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br label %9
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18:
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%19 = add i32 %5, 1
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br label %4
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20:
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ret void
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}
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; CHECK-LABEL: multi_latch
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; CHECK-NOT: call void @llvm.set.loop.iterations
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; CHECK-NOT: call i32 @llvm.loop.decrement
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define void @multi_latch(i32* %a, i32* %b, i32 %N) {
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entry:
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%half = lshr i32 %N, 1
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br label %header
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header:
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%iv = phi i32 [ 0, %entry ], [ %count.next, %latch.0 ], [ %count.next, %latch.1 ]
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%cmp = icmp ult i32 %iv, %half
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%addr.a = getelementptr i32, i32* %a, i32 %iv
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%addr.b = getelementptr i32, i32* %b, i32 %iv
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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store i32 %iv, i32* %addr.a
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br label %latch.0
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if.else:
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store i32 %iv, i32* %addr.b
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br label %latch.0
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latch.0:
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%count.next = add nuw i32 %iv, 1
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%cmp.1 = icmp ult i32 %count.next, %half
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br i1 %cmp.1, label %header, label %latch.1
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latch.1:
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%ld = load i32, i32* %addr.a
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store i32 %ld, i32* %addr.b
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%cmp.2 = icmp ult i32 %count.next, %N
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br i1 %cmp.2, label %header, label %latch.1
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exit:
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ret void
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}
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declare void @llvm.set.loop.iterations.i32(i32) #0
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
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@ -0,0 +1,46 @@
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; RUN: opt -force-hardware-loops=true -hardware-loop-decrement=1 -hardware-loop-counter-bitwidth=32 -hardware-loops -S %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ALLOW
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; RUN: opt -force-hardware-loops=true -hardware-loop-decrement=1 -hardware-loop-counter-bitwidth=32 -force-hardware-loop-phi=true -hardware-loops -S %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LATCH
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; CHECK-LABEL: not_rotated
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; CHECK-LATCH-NOT: call void @llvm.set.loop.iterations
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; CHECK-LATCH-NOT: call i1 @llvm.loop.decrement
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; CHECK-ALLOW: call void @llvm.set.loop.iterations.i32(i32 %4)
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; CHECK-ALLOW: br label %10
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; CHECK-ALLOW: [[CMP:%[^ ]+]] = call i1 @llvm.loop.decrement.i32(i32 1)
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; CHECK-ALLOW: br i1 [[CMP]], label %13, label %19
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define void @not_rotated(i32, i16* nocapture, i16 signext) {
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br label %4
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4:
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%5 = phi i32 [ 0, %3 ], [ %19, %18 ]
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%6 = icmp eq i32 %5, %0
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br i1 %6, label %20, label %7
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7:
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%8 = mul i32 %5, %0
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br label %9
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9:
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%10 = phi i32 [ %17, %12 ], [ 0, %7 ]
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%11 = icmp eq i32 %10, %0
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br i1 %11, label %18, label %12
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12:
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%13 = add i32 %10, %8
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%14 = getelementptr inbounds i16, i16* %1, i32 %13
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%15 = load i16, i16* %14, align 2
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%16 = add i16 %15, %2
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store i16 %16, i16* %14, align 2
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%17 = add i32 %10, 1
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br label %9
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18:
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%19 = add i32 %5, 1
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br label %4
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20:
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ret void
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}
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