[x86] remove RUNs that were checking fully optimized IR
Clang regression tests that depend on the optimizer can break when there are changes to LLVM...as in: https://reviews.llvm.org/rL314117 llvm-svn: 314144
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Sanjay Patel
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@ -1,9 +1,5 @@
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// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512f -emit-llvm -o - -Wall -Werror | FileCheck %s
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// FIXME: It's wrong to check LLVM IR transformations from clang. This run should be removed and tests added to the appropriate LLVM pass.
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// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512f -O2 -emit-llvm -o - -Wall -Werror | FileCheck %s -check-prefix=O2
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#include <immintrin.h>
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__m512d test_mm512_sqrt_pd(__m512d a)
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@ -8309,138 +8305,95 @@ __m512d test_mm512_setzero_pd()
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__mmask16 test_mm512_int2mask(int __a)
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{
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// O2-LABEL: test_mm512_int2mask
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// O2: trunc i32 %__a to i16
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// CHECK-LABEL: test_mm512_int2mask
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// CHECK: trunc i32 %1 to i16
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return _mm512_int2mask(__a);
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}
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int test_mm512_mask2int(__mmask16 __a)
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{
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// O2-LABEL: test_mm512_mask2int
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// O2: zext i16 %__a to i32
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// CHECK-LABEL: test_mm512_mask2int
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// CHECK: zext i16 %1 to i32
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return _mm512_mask2int(__a);
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}
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__m128 test_mm_mask_move_ss (__m128 __W, __mmask8 __U, __m128 __A, __m128 __B)
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{
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// O2-LABEL: @test_mm_mask_move_ss
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// O2: %[[M:.*]] = and i8 %__U, 1
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// O2: %[[M2:.*]] = icmp
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// O2: %[[ELM1:.*]] = extractelement <4 x float>
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// O2: %[[ELM2:.*]] = extractelement <4 x float>
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// O2: %[[SEL:.*]] = select i1 %[[M2]]
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// O2: %[[RES:.*]] = insertelement <4 x float> %__A, float %[[SEL]], i32 0
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// O2: ret <4 x float> %[[RES]]
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// CHECK-LABEL: @test_mm_mask_move_ss
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// CHECK: %vecext.i = extractelement <4 x float> %6, i32 0
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// CHECK: %vecext1.i = extractelement <4 x float> %7, i32 0
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// CHECK: %cond.i = phi float [ %vecext.i, %cond.true.i ], [ %vecext1.i, %cond.false.i ]
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// CHECK: %vecins.i = insertelement <4 x float> %8, float %cond.i, i32 0
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return _mm_mask_move_ss ( __W, __U, __A, __B);
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}
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__m128 test_mm_maskz_move_ss (__mmask8 __U, __m128 __A, __m128 __B)
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{
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// O2-LABEL: @test_mm_maskz_move_ss
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// O2: %[[M:.*]] = and i8 %__U, 1
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// O2: %[[M2:.*]] = icmp
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// O2: %[[ELM1:.*]] = extractelement <4 x float> %__B, i32 0
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// O2: %[[SEL:.*]] = select i1 %[[M2]]
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// O2: %[[RES:.*]] = insertelement <4 x float> %__A, float %[[SEL]], i32 0
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// O2: ret <4 x float> %[[RES]]
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// CHECK-LABEL: @test_mm_maskz_move_ss
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// CHECK: %vecext.i = extractelement <4 x float> %5, i32 0
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// CHECK: %cond.i = phi float [ %vecext.i, %cond.true.i ], [ 0.000000e+00, %cond.false.i ]
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// CHECK: %vecins.i = insertelement <4 x float> %6, float %cond.i, i32 0
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return _mm_maskz_move_ss (__U, __A, __B);
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}
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__m128d test_mm_mask_move_sd (__m128d __W, __mmask8 __U, __m128d __A, __m128d __B)
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{
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// O2-LABEL: @test_mm_mask_move_sd
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// O2: %[[M:.*]] = and i8 %__U, 1
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// O2: %[[M2:.*]] = icmp
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// O2: %[[ELM1:.*]] = extractelement <2 x double>
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// O2: %[[ELM2:.*]] = extractelement <2 x double>
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// O2: %[[SEL:.*]] = select i1 %[[M2]]
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// O2: %[[RES:.*]] = insertelement <2 x double> %__A, double %[[SEL]], i32 0
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// O2: ret <2 x double> %[[RES]]
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// CHECK-LABEL: @test_mm_mask_move_sd
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// CHECK: %vecext.i = extractelement <2 x double> %6, i32 0
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// CHECK: %vecext1.i = extractelement <2 x double> %7, i32 0
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// CHECK: %cond.i = phi double [ %vecext.i, %cond.true.i ], [ %vecext1.i, %cond.false.i ]
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// CHECK: %vecins.i = insertelement <2 x double> %8, double %cond.i, i32 0
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return _mm_mask_move_sd ( __W, __U, __A, __B);
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}
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__m128d test_mm_maskz_move_sd (__mmask8 __U, __m128d __A, __m128d __B)
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{
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// O2-LABEL: @test_mm_maskz_move_sd
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// O2: %[[M:.*]] = and i8 %__U, 1
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// O2: %[[M2:.*]] = icmp
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// O2: %[[ELM1:.*]] = extractelement <2 x double> %__B, i32 0
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// O2: %[[SEL:.*]] = select i1 %[[M2]]
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// O2: %[[RES:.*]] = insertelement <2 x double> %__A, double %[[SEL]], i32 0
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// O2: ret <2 x double> %[[RES]]
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// CHECK-LABEL: @test_mm_maskz_move_sd
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// CHECK: %vecext.i = extractelement <2 x double> %5, i32 0
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// CHECK: %cond.i = phi double [ %vecext.i, %cond.true.i ], [ 0.000000e+00, %cond.false.i ]
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// CHECK: %vecins.i = insertelement <2 x double> %6, double %cond.i, i32 0
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return _mm_maskz_move_sd (__U, __A, __B);
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}
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void test_mm_mask_store_ss(float * __P, __mmask8 __U, __m128 __A)
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{
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// O2-LABEL: @test_mm_mask_store_ss
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// O2: %[[CAST:.*]] = bitcast float* %__P to <16 x float>*
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// O2: %[[SHUFFLE:.*]] = shufflevector <4 x float> %__A, <4 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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// O2: %[[MASK1:.*]] = and i8 %__U, 1
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// O2: %[[MASK2:.*]] = zext i8 %[[MASK1]] to i16
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// O2: %[[MASK3:.*]] = bitcast i16 %[[MASK2]] to <16 x i1>
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// O2: tail call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> %[[SHUFFLE]], <16 x float>* %[[CAST]], i32 16, <16 x i1> %[[MASK3]])
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// CHECK-LABEL: @test_mm_mask_store_ss
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// CHECK: call void @llvm.masked.store.v16f32.p0v16f32(
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_mm_mask_store_ss(__P, __U, __A);
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}
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void test_mm_mask_store_sd(double * __P, __mmask8 __U, __m128d __A)
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{
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// O2-LABEL: @test_mm_mask_store_sd
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// O2: %[[CAST:.*]] = bitcast double* %__P to <8 x double>*
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// O2: %[[SHUFFLE:.*]] = shufflevector <2 x double> %__A, <2 x double> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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// O2: %[[MASK1:.*]] = and i8 %__U, 1
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// O2: %[[MASK2:.*]] = bitcast i8 %[[MASK1]] to <8 x i1>
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// O2: tail call void @llvm.masked.store.v8f64.p0v8f64(<8 x double> %[[SHUFFLE]], <8 x double>* %[[CAST]], i32 16, <8 x i1> %[[MASK2]])
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// CHECK-LABEL: @test_mm_mask_store_sd
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// CHECK: call void @llvm.masked.store.v8f64.p0v8f64(
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_mm_mask_store_sd(__P, __U, __A);
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}
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__m128 test_mm_mask_load_ss(__m128 __A, __mmask8 __U, const float* __W)
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{
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// O2-LABEL: @test_mm_mask_load_ss
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// O2: %[[SHUF:.*]] = shufflevector <4 x float> %__A, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 4>
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// O2: %[[PTR:.*]] = bitcast float* %__W to <16 x float>*
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// O2: %[[SHUF2:.*]] = shufflevector <4 x float> %[[SHUF]], <4 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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// O2: %[[AND:.*]] = and i8 %__U, 1
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// O2: %[[MASK:.*]] = zext i8 %[[AND]] to i16
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// O2: %[[MASK2:.*]] = bitcast i16 %[[MASK]] to <16 x i1>
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// O2: %[[RES:.*]] = tail call <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>* %[[PTR]], i32 16, <16 x i1> %[[MASK2]], <16 x float> %[[SHUF2]])
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// O2: shufflevector <16 x float> %[[RES]], <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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// CHECK-LABEL: @test_mm_mask_load_ss
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// CHECK: call <16 x float> @llvm.masked.load.v16f32.p0v16f32(
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return _mm_mask_load_ss(__A, __U, __W);
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}
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__m128 test_mm_maskz_load_ss (__mmask8 __U, const float * __W)
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{
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// O2-LABEL: @test_mm_maskz_load_ss
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// O2: %[[PTR:.*]] = bitcast float* %__W to <16 x float>*
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// O2: %[[AND:.*]] = and i8 %__U, 1
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// O2: %[[MASK:.*]] = zext i8 %[[AND]] to i16
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// O2: %[[MASK2:.*]] = bitcast i16 %[[MASK]] to <16 x i1>
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// O2: %[[RES:.*]] = tail call <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>* %[[PTR]], i32 16, <16 x i1> %[[MASK2]], <16 x float> zeroinitializer)
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// O2: shufflevector <16 x float> %[[RES]], <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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// CHECK-LABEL: @test_mm_maskz_load_ss
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// CHECK: call <16 x float> @llvm.masked.load.v16f32.p0v16f32(
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return _mm_maskz_load_ss (__U, __W);
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}
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__m128d test_mm_mask_load_sd (__m128d __A, __mmask8 __U, const double * __W)
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{
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// O2-LABEL: @test_mm_mask_load_sd
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// O2: %[[SHUF:.*]] = insertelement <2 x double> %__A, double 0.000000e+00, i32 1
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// O2: %[[PTR:.*]] = bitcast double* %__W to <8 x double>*
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// O2: %[[SHUF2:.*]] = shufflevector <2 x double> %[[SHUF]], <2 x double> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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// O2: %[[AND:.*]] = and i8 %__U, 1
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// O2: %[[MASK:.*]] = bitcast i8 %[[AND]] to <8 x i1>
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// O2: %[[RES:.*]] = tail call <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>* %[[PTR]], i32 16, <8 x i1> %[[MASK]], <8 x double> %[[SHUF2]])
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// O2: shufflevector <8 x double> %[[RES]], <8 x double> undef, <2 x i32> <i32 0, i32 1>
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// CHECK-LABEL: @test_mm_mask_load_sd
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// CHECK: call <8 x double> @llvm.masked.load.v8f64.p0v8f64(
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return _mm_mask_load_sd (__A, __U, __W);
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}
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__m128d test_mm_maskz_load_sd (__mmask8 __U, const double * __W)
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{
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// O2-LABEL: @test_mm_maskz_load_sd
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// O2: %[[PTR:.*]] = bitcast double* %__W to <8 x double>*
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// O2: %[[AND:.*]] = and i8 %__U, 1
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// O2: %[[MASK:.*]] = bitcast i8 %[[AND]] to <8 x i1>
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// O2: %[[RES:.*]] = tail call <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>* %[[PTR]], i32 16, <8 x i1> %[[MASK]], <8 x double> zeroinitializer)
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// O2: shufflevector <8 x double> %[[RES]], <8 x double> undef, <2 x i32> <i32 0, i32 1>
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// CHECK-LABEL: @test_mm_maskz_load_sd
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// CHECK: call <8 x double> @llvm.masked.load.v8f64.p0v8f64(
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return _mm_maskz_load_sd (__U, __W);
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}
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