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Add support for legalization of vector trunc-store where the saved scalar type is illegal (for example, v2i16 on systems where the smallest store size is i32) 

llvm-svn: 141661
This commit is contained in:
Nadav Rotem 2011-10-11 11:25:16 +00:00
parent b521b6037b
commit 198fe81571
1 changed files with 13 additions and 13 deletions
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18
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -1618,13 +1618,13 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
bool RegScalarLegal = TLI.isTypeLegal(RegSclVT);
bool MemScalarLegal = TLI.isTypeLegal(MemSclVT);
// We need to expand this store. If both the reg-scalar and the
// memory-scalar are of legal types, then scalarize the vector.
if (RegScalarLegal && MemScalarLegal) {
// We need to expand this store. If the register element type
// is legal then we can scalarize the vector and use
// truncating stores.
if (RegScalarLegal) {
// Cast floats into integers
unsigned ScalarSize = MemSclVT.getSizeInBits();
EVT EltVT = EVT::getIntegerVT(*DAG.getContext(), ScalarSize);
assert(TLI.isTypeLegal(EltVT) && "Saved scalars must be legal");
// Round odd types to the next pow of two.
if (!isPowerOf2_32(ScalarSize))
@ -1639,13 +1639,15 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
RegSclVT, Tmp3, DAG.getIntPtrConstant(Idx));
Ex = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ex);
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
DAG.getIntPtrConstant(Stride));
SDValue Store = DAG.getStore(Tmp1, dl, Ex, Tmp2,
ST->getPointerInfo().getWithOffset(Idx*Stride),
// This scalar TruncStore may be illegal, but we lehalize it
// later.
SDValue Store = DAG.getTruncStore(Tmp1, dl, Ex, Tmp2,
ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
isVolatile, isNonTemporal, Alignment);
Stores.push_back(Store);
}
@ -1654,7 +1656,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
break;
}
// The scalar register type is illegal.
// For example saving <2 x i64> -> <2 x i32> on a x86.
// In here we bitcast the value into a vector of smaller parts and
@ -1699,7 +1700,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
break;
}
assert(false && "Unable to legalize the vector trunc store!");
}// is vector