[Power9]Legalize and emit code for converting (Un)Signed Word to Quad-Precision
Legalize and emit code for converting (Un)Signed Word to quad-precision via: xscvsdqp xscvudqp Differential Revision: https://reviews.llvm.org/D45389 llvm-svn: 330273
This commit is contained in:
Lei Huang
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e36c67b35c
commit
198e678576
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@ -2514,11 +2514,20 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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def XSCVSDQP : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>;
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def : Pat<(f128 (sint_to_fp i64:$src)),
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(f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
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def XSCVUDQP : X_VT5_XO5_VB5_TyVB<63, 2, 836, "xscvudqp", vfrc, []>;
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def : Pat<(f128 (uint_to_fp i64:$src)),
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(f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
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// Convert (Un)Signed Word -> QP
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def : Pat<(f128 (sint_to_fp i32:$src)),
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(f128 (XSCVSDQP (MTVSRWA $src)))>;
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def : Pat<(f128 (sint_to_fp (i32 (load xoaddr:$src)))),
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(f128 (XSCVSDQP (LIWAX xoaddr:$src)))>;
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def : Pat<(f128 (uint_to_fp i32:$src)),
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(f128 (XSCVUDQP (MTVSRWZ $src)))>;
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def : Pat<(f128 (uint_to_fp (i32 (load xoaddr:$src)))),
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(f128 (XSCVUDQP (LIWZX xoaddr:$src)))>;
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let UseVSXReg = 1 in {
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//===--------------------------------------------------------------------===//
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// Round to Floating-Point Integer Instructions
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@ -1,9 +1,11 @@
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr < %s | FileCheck %s
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; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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@mem = global [5 x i64] [i64 56, i64 63, i64 3, i64 5, i64 6], align 8
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@umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
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@swMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
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@uwMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
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; Function Attrs: norecurse nounwind
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define void @sdwConv2qp(fp128* nocapture %a, i64 %b) {
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@ -138,3 +140,160 @@ entry:
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @swConv2qp(fp128* nocapture %a, i32 signext %b) {
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entry:
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%conv = sitofp i32 %b to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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; CHECK-LABEL: swConv2qp
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; CHECK-NOT: lwz
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; CHECK: mtvsrwa [[REG0:[0-9]+]], 4
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; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG1]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @swConv2qp_02(fp128* nocapture %a, i32* nocapture readonly %b) {
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entry:
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%0 = load i32, i32* %b, align 4
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%conv = sitofp i32 %0 to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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; CHECK-LABEL: swConv2qp_02
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; CHECK-NOT: lwz
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; CHECK: lxsiwax [[REG:[0-9]+]], 0, 4
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; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @swConv2qp_03(fp128* nocapture %a) {
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entry:
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%0 = load i32, i32* getelementptr inbounds
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([5 x i32], [5 x i32]* @swMem, i64 0, i64 3), align 4
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%conv = sitofp i32 %0 to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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; CHECK-LABEL: swConv2qp_03
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; CHECK: addis [[REG:[0-9]+]], 2, .LC2@toc@ha
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; CHECK: ld [[REG]], .LC2@toc@l([[REG]])
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; CHECK: addi [[REG2:[0-9]+]], [[REG]], 12
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; CHECK: lxsiwax [[REG0:[0-9]+]], 0, [[REG2]]
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; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG0]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @uwConv2qp(fp128* nocapture %a, i32 zeroext %b) {
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entry:
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%conv = uitofp i32 %b to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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; CHECK-LABEL: uwConv2qp
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; CHECK-NOT: lwz
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; CHECK: mtvsrwz [[REG:[0-9]+]], 4
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; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @uwConv2qp_02(fp128* nocapture %a, i32* nocapture readonly %b) {
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entry:
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%0 = load i32, i32* %b, align 4
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%conv = uitofp i32 %0 to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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; CHECK-LABEL: uwConv2qp_02
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; CHECK-NOT: lwz
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; CHECK: lxsiwzx [[REG:[0-9]+]], 0, 4
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; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @uwConv2qp_03(fp128* nocapture %a) {
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entry:
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%0 = load i32, i32* getelementptr inbounds
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([5 x i32], [5 x i32]* @uwMem, i64 0, i64 3), align 4
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%conv = uitofp i32 %0 to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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; CHECK-LABEL: uwConv2qp_03
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; CHECK: addis [[REG:[0-9]+]], 2, .LC3@toc@ha
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; CHECK-NEXT: ld [[REG]], .LC3@toc@l([[REG]])
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; CHECK-NEXT: addi [[REG2:[0-9]+]], [[REG]], 12
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; CHECK-NEXT: lxsiwzx [[REG1:[0-9]+]], 0, [[REG2]]
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; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG1]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @uwConv2qp_04(fp128* nocapture %a,
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i32 zeroext %b, i32* nocapture readonly %c) {
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entry:
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%0 = load i32, i32* %c, align 4
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%add = add i32 %0, %b
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%conv = uitofp i32 %add to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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; CHECK-LABEL: uwConv2qp_04
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; CHECK: lwz [[REG:[0-9]+]], 0(5)
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; CHECK-NEXT: add [[REG1:[0-9]+]], [[REG]], [[REG1]]
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; CHECK-NEXT: mtvsrwz [[REG0:[0-9]+]], [[REG1]]
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; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG0]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @swConv2qp_testXForm(fp128* nocapture %sink,
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i8* nocapture readonly %a) {
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entry:
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%add.ptr = getelementptr inbounds i8, i8* %a, i64 3
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%0 = bitcast i8* %add.ptr to i32*
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%1 = load i32, i32* %0, align 4
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%conv = sitofp i32 %1 to fp128
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store fp128 %conv, fp128* %sink, align 16
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ret void
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; CHECK-LABEL: swConv2qp_testXForm
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; CHECK: addi [[REG:[0-9]+]], 4, 3
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; CHECK-NEXT: lxsiwax [[REG1:[0-9]+]], 0, [[REG]]
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; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG1]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @uwConv2qp_testXForm(fp128* nocapture %sink,
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i8* nocapture readonly %a) {
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entry:
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%add.ptr = getelementptr inbounds i8, i8* %a, i64 3
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%0 = bitcast i8* %add.ptr to i32*
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%1 = load i32, i32* %0, align 4
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%conv = uitofp i32 %1 to fp128
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store fp128 %conv, fp128* %sink, align 16
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ret void
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; CHECK-LABEL: uwConv2qp_testXForm
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; CHECK: addi [[REG:[0-9]+]], 4, 3
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; CHECK-NEXT: lxsiwzx [[REG1:[0-9]+]], 0, [[REG]]
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; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG1]]
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; CHECK-NEXT: stxv [[CONV]], 0(3)
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; CHECK-NEXT: blr
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}
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