Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
llvm-svn: 134030
This commit is contained in:
parent
4e77f6f499
commit
194c3dc01f
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@ -44,7 +44,9 @@ class TargetInstrInfo : public MCInstrInfo {
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TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
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TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
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void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
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void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
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public:
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public:
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TargetInstrInfo(const MCInstrDesc *desc, unsigned NumOpcodes);
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TargetInstrInfo(const MCInstrDesc *desc, unsigned NumOpcodes,
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int CallFrameSetupOpcode = -1,
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int CallFrameDestroyOpcode = -1);
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virtual ~TargetInstrInfo();
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virtual ~TargetInstrInfo();
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/// getRegClass - Givem a machine instruction descriptor, returns the register
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/// getRegClass - Givem a machine instruction descriptor, returns the register
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@ -86,6 +88,15 @@ private:
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AliasAnalysis *AA) const;
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AliasAnalysis *AA) const;
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public:
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public:
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/// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
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/// frame setup/destroy instructions if they exist (-1 otherwise). Some
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/// targets use pseudo instructions in order to abstract away the difference
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/// between operating with a frame pointer and operating without, through the
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/// use of these two instructions.
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///
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int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
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int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
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/// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
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/// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
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/// extension instruction. That is, it's like a copy where it's legal for the
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/// extension instruction. That is, it's like a copy where it's legal for the
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/// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
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/// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
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@ -656,6 +667,9 @@ public:
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virtual
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virtual
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bool hasLowDefLatency(const InstrItineraryData *ItinData,
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bool hasLowDefLatency(const InstrItineraryData *ItinData,
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const MachineInstr *DefMI, unsigned DefIdx) const;
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const MachineInstr *DefMI, unsigned DefIdx) const;
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private:
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int CallFrameSetupOpcode, CallFrameDestroyOpcode;
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};
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};
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/// TargetInstrInfoImpl - This is the default implementation of
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/// TargetInstrInfoImpl - This is the default implementation of
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@ -664,7 +678,9 @@ public:
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/// libcodegen, not in libtarget.
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/// libcodegen, not in libtarget.
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class TargetInstrInfoImpl : public TargetInstrInfo {
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class TargetInstrInfoImpl : public TargetInstrInfo {
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protected:
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protected:
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TargetInstrInfoImpl(const MCInstrDesc *desc, unsigned NumOpcodes)
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TargetInstrInfoImpl(const MCInstrDesc *desc, unsigned NumOpcodes,
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int CallFrameSetupOpcode = -1,
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int CallFrameDestroyOpcode = -1)
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: TargetInstrInfo(desc, NumOpcodes) {}
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: TargetInstrInfo(desc, NumOpcodes) {}
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public:
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public:
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virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
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virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
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@ -275,15 +275,12 @@ private:
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const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
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const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
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const char *const *SubRegIndexNames; // Names of subreg indexes.
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const char *const *SubRegIndexNames; // Names of subreg indexes.
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regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
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regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
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int CallFrameSetupOpcode, CallFrameDestroyOpcode;
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protected:
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protected:
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TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
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TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
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regclass_iterator RegClassBegin,
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regclass_iterator RegClassBegin,
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regclass_iterator RegClassEnd,
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regclass_iterator RegClassEnd,
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const char *const *subregindexnames,
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const char *const *subregindexnames);
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int CallFrameSetupOpcode = -1,
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int CallFrameDestroyOpcode = -1);
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virtual ~TargetRegisterInfo();
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virtual ~TargetRegisterInfo();
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public:
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public:
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@ -661,15 +658,6 @@ public:
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return false; // Must return a value in order to compile with VS 2005
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return false; // Must return a value in order to compile with VS 2005
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}
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}
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/// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
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/// frame setup/destroy instructions if they exist (-1 otherwise). Some
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/// targets use pseudo instructions in order to abstract away the difference
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/// between operating with a frame pointer and operating without, through the
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/// use of these two instructions.
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///
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int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
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int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
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/// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
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/// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
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/// code insertion to eliminate call frame setup and destroy pseudo
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/// code insertion to eliminate call frame setup and destroy pseudo
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/// instructions (but only if the Target is using them). It is responsible
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/// instructions (but only if the Target is using them). It is responsible
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@ -681,9 +669,6 @@ public:
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eliminateCallFramePseudoInstr(MachineFunction &MF,
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eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const {
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MachineBasicBlock::iterator MI) const {
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assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
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"eliminateCallFramePseudoInstr must be implemented if using"
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" call frame setup/destroy pseudo instructions!");
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assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
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assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
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}
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}
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@ -145,6 +145,7 @@ void PEI::getAnalysisUsage(AnalysisUsage &AU) const {
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/// pseudo instructions.
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/// pseudo instructions.
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void PEI::calculateCallsInformation(MachineFunction &Fn) {
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void PEI::calculateCallsInformation(MachineFunction &Fn) {
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const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
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const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
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const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
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const TargetFrameLowering *TFI = Fn.getTarget().getFrameLowering();
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const TargetFrameLowering *TFI = Fn.getTarget().getFrameLowering();
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MachineFrameInfo *MFI = Fn.getFrameInfo();
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MachineFrameInfo *MFI = Fn.getFrameInfo();
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@ -152,8 +153,8 @@ void PEI::calculateCallsInformation(MachineFunction &Fn) {
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bool AdjustsStack = MFI->adjustsStack();
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bool AdjustsStack = MFI->adjustsStack();
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// Get the function call frame set-up and tear-down instruction opcode
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// Get the function call frame set-up and tear-down instruction opcode
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int FrameSetupOpcode = RegInfo->getCallFrameSetupOpcode();
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int FrameSetupOpcode = TII.getCallFrameSetupOpcode();
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int FrameDestroyOpcode = RegInfo->getCallFrameDestroyOpcode();
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int FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
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// Early exit for targets which have no call frame setup/destroy pseudo
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// Early exit for targets which have no call frame setup/destroy pseudo
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// instructions.
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// instructions.
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@ -705,12 +706,13 @@ void PEI::replaceFrameIndices(MachineFunction &Fn) {
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const TargetMachine &TM = Fn.getTarget();
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const TargetMachine &TM = Fn.getTarget();
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assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
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assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
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const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
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const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
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const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
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const TargetFrameLowering *TFI = TM.getFrameLowering();
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const TargetFrameLowering *TFI = TM.getFrameLowering();
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bool StackGrowsDown =
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bool StackGrowsDown =
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TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
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TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
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int FrameSetupOpcode = TRI.getCallFrameSetupOpcode();
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int FrameSetupOpcode = TII.getCallFrameSetupOpcode();
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int FrameDestroyOpcode = TRI.getCallFrameDestroyOpcode();
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int FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
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for (MachineFunction::iterator BB = Fn.begin(),
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for (MachineFunction::iterator BB = Fn.begin(),
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E = Fn.end(); BB != E; ++BB) {
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E = Fn.end(); BB != E; ++BB) {
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@ -77,7 +77,8 @@ static const ARM_MLxEntry ARM_MLxTable[] = {
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};
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};
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ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
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ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
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: TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
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: TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts),
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ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
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Subtarget(STI) {
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Subtarget(STI) {
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for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
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for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
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if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
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if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
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@ -58,8 +58,7 @@ EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
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ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
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ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
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const ARMSubtarget &sti)
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const ARMSubtarget &sti)
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: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
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: ARMGenRegisterInfo(), TII(tii), STI(sti),
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TII(tii), STI(sti),
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FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
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FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
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BasePtr(ARM::R6) {
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BasePtr(ARM::R6) {
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}
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}
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@ -1549,7 +1549,7 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
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NumBytes = CCInfo.getNextStackOffset();
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NumBytes = CCInfo.getNextStackOffset();
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// Issue CALLSEQ_START
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// Issue CALLSEQ_START
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unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
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unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(AdjStackDown))
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TII.get(AdjStackDown))
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.addImm(NumBytes));
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.addImm(NumBytes));
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@ -1647,7 +1647,7 @@ bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
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const Instruction *I, CallingConv::ID CC,
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const Instruction *I, CallingConv::ID CC,
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unsigned &NumBytes) {
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unsigned &NumBytes) {
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// Issue CALLSEQ_END
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// Issue CALLSEQ_END
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unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
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unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(AdjStackUp))
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TII.get(AdjStackUp))
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.addImm(NumBytes).addImm(0));
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.addImm(NumBytes).addImm(0));
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@ -25,7 +25,8 @@
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using namespace llvm;
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using namespace llvm;
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AlphaInstrInfo::AlphaInstrInfo()
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AlphaInstrInfo::AlphaInstrInfo()
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: TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts)),
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: TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts),
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Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
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RI(*this) { }
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RI(*this) { }
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using namespace llvm;
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using namespace llvm;
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AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
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AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
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: AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
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: AlphaGenRegisterInfo(),
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TII(tii) {
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TII(tii) {
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}
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}
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@ -26,7 +26,8 @@
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using namespace llvm;
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using namespace llvm;
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BlackfinInstrInfo::BlackfinInstrInfo(BlackfinSubtarget &ST)
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BlackfinInstrInfo::BlackfinInstrInfo(BlackfinSubtarget &ST)
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: TargetInstrInfoImpl(BlackfinInsts, array_lengthof(BlackfinInsts)),
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: TargetInstrInfoImpl(BlackfinInsts, array_lengthof(BlackfinInsts),
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BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
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RI(ST, *this),
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RI(ST, *this),
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Subtarget(ST) {}
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Subtarget(ST) {}
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BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
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BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
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const TargetInstrInfo &tii)
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const TargetInstrInfo &tii)
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: BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
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: BlackfinGenRegisterInfo(), Subtarget(st), TII(tii) {}
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Subtarget(st),
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TII(tii) {}
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const unsigned*
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const unsigned*
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BlackfinRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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BlackfinRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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@ -53,7 +53,8 @@ namespace {
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}
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}
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SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
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SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
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: TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
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: TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0]),
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SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
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TM(tm),
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TM(tm),
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RI(*TM.getSubtargetImpl(), *this)
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RI(*TM.getSubtargetImpl(), *this)
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{ /* NOP */ }
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{ /* NOP */ }
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@ -189,9 +189,7 @@ unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
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SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
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SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
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const TargetInstrInfo &tii) :
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const TargetInstrInfo &tii) :
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SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
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SPUGenRegisterInfo(), Subtarget(subtarget), TII(tii)
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Subtarget(subtarget),
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TII(tii)
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{
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{
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}
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}
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@ -27,7 +27,8 @@
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using namespace llvm;
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using namespace llvm;
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MBlazeInstrInfo::MBlazeInstrInfo(MBlazeTargetMachine &tm)
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MBlazeInstrInfo::MBlazeInstrInfo(MBlazeTargetMachine &tm)
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: TargetInstrInfoImpl(MBlazeInsts, array_lengthof(MBlazeInsts)),
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: TargetInstrInfoImpl(MBlazeInsts, array_lengthof(MBlazeInsts),
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MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
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TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
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TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
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static bool isZeroImm(const MachineOperand &op) {
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static bool isZeroImm(const MachineOperand &op) {
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@ -45,8 +45,7 @@ using namespace llvm;
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MBlazeRegisterInfo::
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MBlazeRegisterInfo::
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MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
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MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
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: MBlazeGenRegisterInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
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: MBlazeGenRegisterInfo(), Subtarget(ST), TII(tii) {}
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Subtarget(ST), TII(tii) {}
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// MBlaze::R0, return the number that it corresponds to (e.g. 0).
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/// MBlaze::R0, return the number that it corresponds to (e.g. 0).
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@ -28,7 +28,8 @@
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using namespace llvm;
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using namespace llvm;
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MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
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MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
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: TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)),
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: TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts),
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MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
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RI(tm, *this), TM(tm) {}
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RI(tm, *this), TM(tm) {}
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void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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@ -35,8 +35,7 @@ using namespace llvm;
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// FIXME: Provide proper call frame setup / destroy opcodes.
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// FIXME: Provide proper call frame setup / destroy opcodes.
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MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
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MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
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const TargetInstrInfo &tii)
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const TargetInstrInfo &tii)
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: MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
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: MSP430GenRegisterInfo(), TM(tm), TII(tii) {
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TM(tm), TII(tii) {
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StackAlign = TM.getFrameLowering()->getStackAlignment();
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StackAlign = TM.getFrameLowering()->getStackAlignment();
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}
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}
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@ -121,12 +120,12 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
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Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
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||||||
MachineInstr *New = 0;
|
MachineInstr *New = 0;
|
||||||
if (Old->getOpcode() == getCallFrameSetupOpcode()) {
|
if (Old->getOpcode() == TII.getCallFrameSetupOpcode()) {
|
||||||
New = BuildMI(MF, Old->getDebugLoc(),
|
New = BuildMI(MF, Old->getDebugLoc(),
|
||||||
TII.get(MSP430::SUB16ri), MSP430::SPW)
|
TII.get(MSP430::SUB16ri), MSP430::SPW)
|
||||||
.addReg(MSP430::SPW).addImm(Amount);
|
.addReg(MSP430::SPW).addImm(Amount);
|
||||||
} else {
|
} else {
|
||||||
assert(Old->getOpcode() == getCallFrameDestroyOpcode());
|
assert(Old->getOpcode() == TII.getCallFrameDestroyOpcode());
|
||||||
// factor out the amount the callee already popped.
|
// factor out the amount the callee already popped.
|
||||||
uint64_t CalleeAmt = Old->getOperand(1).getImm();
|
uint64_t CalleeAmt = Old->getOperand(1).getImm();
|
||||||
Amount -= CalleeAmt;
|
Amount -= CalleeAmt;
|
||||||
|
@ -144,7 +143,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||||
MBB.insert(I, New);
|
MBB.insert(I, New);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
} else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
|
} else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) {
|
||||||
// If we are performing frame pointer elimination and if the callee pops
|
// If we are performing frame pointer elimination and if the callee pops
|
||||||
// something off the stack pointer, add it back.
|
// something off the stack pointer, add it back.
|
||||||
if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
|
if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
|
||||||
|
|
|
@ -25,7 +25,8 @@
|
||||||
using namespace llvm;
|
using namespace llvm;
|
||||||
|
|
||||||
MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
|
MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
|
||||||
: TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
|
: TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts),
|
||||||
|
Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
|
||||||
TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
|
TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
|
||||||
|
|
||||||
static bool isZeroImm(const MachineOperand &op) {
|
static bool isZeroImm(const MachineOperand &op) {
|
||||||
|
|
|
@ -44,8 +44,7 @@ using namespace llvm;
|
||||||
|
|
||||||
MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
|
MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
|
||||||
const TargetInstrInfo &tii)
|
const TargetInstrInfo &tii)
|
||||||
: MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
|
: MipsGenRegisterInfo(), Subtarget(ST), TII(tii) {}
|
||||||
Subtarget(ST), TII(tii) {}
|
|
||||||
|
|
||||||
/// getRegisterNumbering - Given the enum value for some register, e.g.
|
/// getRegisterNumbering - Given the enum value for some register, e.g.
|
||||||
/// Mips::RA, return the number that it corresponds to (e.g. 31).
|
/// Mips::RA, return the number that it corresponds to (e.g. 31).
|
||||||
|
|
|
@ -39,8 +39,9 @@ extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
|
||||||
using namespace llvm;
|
using namespace llvm;
|
||||||
|
|
||||||
PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
|
PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
|
||||||
: TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
|
: TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts),
|
||||||
RI(*TM.getSubtargetImpl(), *this) {}
|
PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
|
||||||
|
TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
|
||||||
|
|
||||||
/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
|
/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
|
||||||
/// this target when scheduling the DAG.
|
/// this target when scheduling the DAG.
|
||||||
|
|
|
@ -114,8 +114,7 @@ unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
|
||||||
|
|
||||||
PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
|
PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
|
||||||
const TargetInstrInfo &tii)
|
const TargetInstrInfo &tii)
|
||||||
: PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
|
: PPCGenRegisterInfo(), Subtarget(ST), TII(tii) {
|
||||||
Subtarget(ST), TII(tii) {
|
|
||||||
ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
|
ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
|
||||||
ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
|
ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
|
||||||
ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
|
ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
|
||||||
|
|
|
@ -27,7 +27,8 @@
|
||||||
using namespace llvm;
|
using namespace llvm;
|
||||||
|
|
||||||
SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
|
SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
|
||||||
: TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)),
|
: TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts),
|
||||||
|
SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
|
||||||
RI(ST, *this), Subtarget(ST) {
|
RI(ST, *this), Subtarget(ST) {
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -32,8 +32,7 @@ using namespace llvm;
|
||||||
|
|
||||||
SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
|
SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
|
||||||
const TargetInstrInfo &tii)
|
const TargetInstrInfo &tii)
|
||||||
: SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
|
: SparcGenRegisterInfo(), Subtarget(st), TII(tii) {
|
||||||
Subtarget(st), TII(tii) {
|
|
||||||
}
|
}
|
||||||
|
|
||||||
const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
|
const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
|
||||||
|
|
|
@ -29,7 +29,8 @@
|
||||||
using namespace llvm;
|
using namespace llvm;
|
||||||
|
|
||||||
SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
|
SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
|
||||||
: TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)),
|
: TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts),
|
||||||
|
SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
|
||||||
RI(tm, *this), TM(tm) {
|
RI(tm, *this), TM(tm) {
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -34,8 +34,7 @@ using namespace llvm;
|
||||||
|
|
||||||
SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
|
SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
|
||||||
const SystemZInstrInfo &tii)
|
const SystemZInstrInfo &tii)
|
||||||
: SystemZGenRegisterInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
|
: SystemZGenRegisterInfo(), TM(tm), TII(tii) {
|
||||||
TM(tm), TII(tii) {
|
|
||||||
}
|
}
|
||||||
|
|
||||||
const unsigned*
|
const unsigned*
|
||||||
|
|
|
@ -24,7 +24,10 @@ using namespace llvm;
|
||||||
// TargetInstrInfo
|
// TargetInstrInfo
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
TargetInstrInfo::TargetInstrInfo(const MCInstrDesc* Desc, unsigned numOpcodes) {
|
TargetInstrInfo::TargetInstrInfo(const MCInstrDesc* Desc, unsigned numOpcodes,
|
||||||
|
int CFSetupOpcode, int CFDestroyOpcode)
|
||||||
|
: CallFrameSetupOpcode(CFSetupOpcode),
|
||||||
|
CallFrameDestroyOpcode(CFDestroyOpcode) {
|
||||||
InitMCInstrInfo(Desc, numOpcodes);
|
InitMCInstrInfo(Desc, numOpcodes);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -22,12 +22,9 @@ using namespace llvm;
|
||||||
|
|
||||||
TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
|
TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
|
||||||
regclass_iterator RCB, regclass_iterator RCE,
|
regclass_iterator RCB, regclass_iterator RCE,
|
||||||
const char *const *subregindexnames,
|
const char *const *subregindexnames)
|
||||||
int CFSO, int CFDO)
|
|
||||||
: InfoDesc(ID), SubRegIndexNames(subregindexnames),
|
: InfoDesc(ID), SubRegIndexNames(subregindexnames),
|
||||||
RegClassBegin(RCB), RegClassEnd(RCE) {
|
RegClassBegin(RCB), RegClassEnd(RCE) {
|
||||||
CallFrameSetupOpcode = CFSO;
|
|
||||||
CallFrameDestroyOpcode = CFDO;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
TargetRegisterInfo::~TargetRegisterInfo() {}
|
TargetRegisterInfo::~TargetRegisterInfo() {}
|
||||||
|
|
|
@ -1630,7 +1630,7 @@ bool X86FastISel::DoSelectCall(const Instruction *I, const char *MemIntName) {
|
||||||
unsigned NumBytes = CCInfo.getNextStackOffset();
|
unsigned NumBytes = CCInfo.getNextStackOffset();
|
||||||
|
|
||||||
// Issue CALLSEQ_START
|
// Issue CALLSEQ_START
|
||||||
unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
|
unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
|
||||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown))
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown))
|
||||||
.addImm(NumBytes);
|
.addImm(NumBytes);
|
||||||
|
|
||||||
|
@ -1803,7 +1803,7 @@ bool X86FastISel::DoSelectCall(const Instruction *I, const char *MemIntName) {
|
||||||
MIB.addReg(RegArgs[i]);
|
MIB.addReg(RegArgs[i]);
|
||||||
|
|
||||||
// Issue CALLSEQ_END
|
// Issue CALLSEQ_END
|
||||||
unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
|
unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
|
||||||
unsigned NumBytesCallee = 0;
|
unsigned NumBytesCallee = 0;
|
||||||
if (!Subtarget->is64Bit() && CS.paramHasAttr(1, Attribute::StructRet))
|
if (!Subtarget->is64Bit() && CS.paramHasAttr(1, Attribute::StructRet))
|
||||||
NumBytesCallee = 4;
|
NumBytesCallee = 4;
|
||||||
|
|
|
@ -54,7 +54,13 @@ ReMatPICStubLoad("remat-pic-stub-load",
|
||||||
cl::init(false), cl::Hidden);
|
cl::init(false), cl::Hidden);
|
||||||
|
|
||||||
X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
|
X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
|
||||||
: TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
|
: TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts),
|
||||||
|
(tm.getSubtarget<X86Subtarget>().is64Bit()
|
||||||
|
? X86::ADJCALLSTACKDOWN64
|
||||||
|
: X86::ADJCALLSTACKDOWN32),
|
||||||
|
(tm.getSubtarget<X86Subtarget>().is64Bit()
|
||||||
|
? X86::ADJCALLSTACKUP64
|
||||||
|
: X86::ADJCALLSTACKUP32)),
|
||||||
TM(tm), RI(tm, *this) {
|
TM(tm), RI(tm, *this) {
|
||||||
enum {
|
enum {
|
||||||
TB_NOT_REVERSABLE = 1U << 31,
|
TB_NOT_REVERSABLE = 1U << 31,
|
||||||
|
|
|
@ -54,13 +54,7 @@ ForceStackAlign("force-align-stack",
|
||||||
|
|
||||||
X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
|
X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
|
||||||
const TargetInstrInfo &tii)
|
const TargetInstrInfo &tii)
|
||||||
: X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
|
: X86GenRegisterInfo(), TM(tm), TII(tii) {
|
||||||
X86::ADJCALLSTACKDOWN64 :
|
|
||||||
X86::ADJCALLSTACKDOWN32,
|
|
||||||
tm.getSubtarget<X86Subtarget>().is64Bit() ?
|
|
||||||
X86::ADJCALLSTACKUP64 :
|
|
||||||
X86::ADJCALLSTACKUP32),
|
|
||||||
TM(tm), TII(tii) {
|
|
||||||
// Cache some information.
|
// Cache some information.
|
||||||
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
|
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
|
||||||
Is64Bit = Subtarget->is64Bit();
|
Is64Bit = Subtarget->is64Bit();
|
||||||
|
@ -608,7 +602,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||||
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
||||||
bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
|
bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
|
||||||
int Opcode = I->getOpcode();
|
int Opcode = I->getOpcode();
|
||||||
bool isDestroy = Opcode == getCallFrameDestroyOpcode();
|
bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
|
||||||
DebugLoc DL = I->getDebugLoc();
|
DebugLoc DL = I->getDebugLoc();
|
||||||
uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
|
uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
|
||||||
uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
|
uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
|
||||||
|
@ -629,13 +623,13 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||||
Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
|
Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
|
||||||
|
|
||||||
MachineInstr *New = 0;
|
MachineInstr *New = 0;
|
||||||
if (Opcode == getCallFrameSetupOpcode()) {
|
if (Opcode == TII.getCallFrameSetupOpcode()) {
|
||||||
New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
|
New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
|
||||||
StackPtr)
|
StackPtr)
|
||||||
.addReg(StackPtr)
|
.addReg(StackPtr)
|
||||||
.addImm(Amount);
|
.addImm(Amount);
|
||||||
} else {
|
} else {
|
||||||
assert(Opcode == getCallFrameDestroyOpcode());
|
assert(Opcode == TII.getCallFrameDestroyOpcode());
|
||||||
|
|
||||||
// Factor out the amount the callee already popped.
|
// Factor out the amount the callee already popped.
|
||||||
Amount -= CalleeAmt;
|
Amount -= CalleeAmt;
|
||||||
|
@ -658,7 +652,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (Opcode == getCallFrameDestroyOpcode() && CalleeAmt) {
|
if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
|
||||||
// If we are performing frame pointer elimination and if the callee pops
|
// If we are performing frame pointer elimination and if the callee pops
|
||||||
// something off the stack pointer, add it back. We do this until we have
|
// something off the stack pointer, add it back. We do this until we have
|
||||||
// more advanced stack pointer tracking ability.
|
// more advanced stack pointer tracking ability.
|
||||||
|
|
|
@ -40,7 +40,8 @@ namespace XCore {
|
||||||
using namespace llvm;
|
using namespace llvm;
|
||||||
|
|
||||||
XCoreInstrInfo::XCoreInstrInfo()
|
XCoreInstrInfo::XCoreInstrInfo()
|
||||||
: TargetInstrInfoImpl(XCoreInsts, array_lengthof(XCoreInsts)),
|
: TargetInstrInfoImpl(XCoreInsts, array_lengthof(XCoreInsts),
|
||||||
|
XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
|
||||||
RI(*this) {
|
RI(*this) {
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -40,8 +40,7 @@
|
||||||
using namespace llvm;
|
using namespace llvm;
|
||||||
|
|
||||||
XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
|
XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
|
||||||
: XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
|
: XCoreGenRegisterInfo(), TII(tii) {
|
||||||
TII(tii) {
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// helper functions
|
// helper functions
|
||||||
|
|
|
@ -214,8 +214,7 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
|
||||||
OS << "namespace llvm {\n\n";
|
OS << "namespace llvm {\n\n";
|
||||||
|
|
||||||
OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
|
OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
|
||||||
<< " explicit " << ClassName
|
<< " explicit " << ClassName << "();\n"
|
||||||
<< "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
|
|
||||||
<< " virtual int getDwarfRegNumFull(unsigned RegNum, "
|
<< " virtual int getDwarfRegNumFull(unsigned RegNum, "
|
||||||
<< "unsigned Flavour) const;\n"
|
<< "unsigned Flavour) const;\n"
|
||||||
<< " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
|
<< " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
|
||||||
|
@ -660,11 +659,10 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
|
||||||
|
|
||||||
// Emit the constructor of the class...
|
// Emit the constructor of the class...
|
||||||
OS << ClassName << "::" << ClassName
|
OS << ClassName << "::" << ClassName
|
||||||
<< "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
|
<< "()\n"
|
||||||
<< " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
|
<< " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
|
||||||
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
|
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
|
||||||
<< " SubRegIndexTable,\n"
|
<< " SubRegIndexTable) {\n"
|
||||||
<< " CallFrameSetupOpcode, CallFrameDestroyOpcode) {\n"
|
|
||||||
<< " InitMCRegisterInfo(" << TargetName << "RegDesc, "
|
<< " InitMCRegisterInfo(" << TargetName << "RegDesc, "
|
||||||
<< Regs.size()+1 << ");\n"
|
<< Regs.size()+1 << ");\n"
|
||||||
<< "}\n\n";
|
<< "}\n\n";
|
||||||
|
|
Loading…
Reference in New Issue