From 18a9d545e16fecca6b7ffe039f86a55f6fb9c022 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@intel.com>
Date: Tue, 18 Dec 2018 20:03:54 +0000
Subject: [PATCH] [X86] Add BSR to isUseDefConvertible.

We already had BSF here as part of __builtin_ffs improvements and I was just wondering yesterday whether we should have BSR there.

This addresses one issue from PR40090.

llvm-svn: 349531
---
 llvm/lib/Target/X86/X86InstrInfo.cpp | 12 ++++++------
 llvm/test/CodeGen/X86/pr40090.ll     | 24 ++++++++++++++++++++++++
 2 files changed, 30 insertions(+), 6 deletions(-)
 create mode 100644 llvm/test/CodeGen/X86/pr40090.ll

diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 98c1a12c7ac7..40de049bfe8b 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3579,12 +3579,12 @@ static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
   case X86::TZCNT32rr: case X86::TZCNT32rm:
   case X86::TZCNT64rr: case X86::TZCNT64rm:
     return X86::COND_B;
-  case X86::BSF16rr:
-  case X86::BSF16rm:
-  case X86::BSF32rr:
-  case X86::BSF32rm:
-  case X86::BSF64rr:
-  case X86::BSF64rm:
+  case X86::BSF16rr: case X86::BSF16rm:
+  case X86::BSF32rr: case X86::BSF32rm:
+  case X86::BSF64rr: case X86::BSF64rm:
+  case X86::BSR16rr: case X86::BSR16rm:
+  case X86::BSR32rr: case X86::BSR32rm:
+  case X86::BSR64rr: case X86::BSR64rm:
     return X86::COND_E;
   }
 }
diff --git a/llvm/test/CodeGen/X86/pr40090.ll b/llvm/test/CodeGen/X86/pr40090.ll
new file mode 100644
index 000000000000..d1c38e4104d7
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr40090.ll
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+define i64 @foo(i64 %x, i64 %y) {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    bsrq %rdi, %rax
+; CHECK-NEXT:    xorq $64, %rax
+; CHECK-NEXT:    bsrq %rsi, %rcx
+; CHECK-NEXT:    cmoveq %rax, %rcx
+; CHECK-NEXT:    movl $63, %eax
+; CHECK-NEXT:    subq %rcx, %rax
+; CHECK-NEXT:    retq
+  %1 = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
+  %2 = xor i64 %1, 127
+  %3 = tail call i64 @llvm.ctlz.i64(i64 %y, i1 true)
+  %4 = xor i64 %3, 63
+  %5 = icmp eq i64 %y, 0
+  %6 = select i1 %5, i64 %2, i64 %4
+  %7 = sub nsw i64 63, %6
+  ret i64 %7
+}
+
+declare i64 @llvm.ctlz.i64(i64, i1)