replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

[x86] use getBitcast() 

This isn't quite NFC because some of the SDLocs may change which could
cause scheduling differences. But no regression tests are affected and
there is no functional change intended.

llvm-svn: 262391
This commit is contained in:
Sanjay Patel 2016-03-01 20:47:02 +00:00
parent bcb1c7e369
commit 18988ae66c
1 changed files with 20 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -5425,7 +5425,7 @@ static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
// Let the shuffle legalizer deal with blend operations. // Let the shuffle legalizer deal with blend operations.
SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op)); SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
if (V1.getSimpleValueType() != VT) if (V1.getSimpleValueType() != VT)
V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1); V1 = DAG.getBitcast(VT, V1);
return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]); return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
} }
@ -5455,9 +5455,9 @@ static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
assert(V1.getNode() && "Expected at least two non-zero elements!"); assert(V1.getNode() && "Expected at least two non-zero elements!");
if (V1.getSimpleValueType() != MVT::v4f32) if (V1.getSimpleValueType() != MVT::v4f32)
V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1); V1 = DAG.getBitcast(MVT::v4f32, V1);
if (V2.getSimpleValueType() != MVT::v4f32) if (V2.getSimpleValueType() != MVT::v4f32)
V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2); V2 = DAG.getBitcast(MVT::v4f32, V2);
// Ok, we can emit an INSERTPS instruction. // Ok, we can emit an INSERTPS instruction.
unsigned ZMask = Zeroable.to_ulong(); unsigned ZMask = Zeroable.to_ulong();
@ -7963,22 +7963,22 @@ static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
assert(VT.is128BitVector() && "Unexpected vector width!"); assert(VT.is128BitVector() && "Unexpected vector width!");
int LoIdx = Offset * EltBits; int LoIdx = Offset * EltBits;
SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, SDValue Lo = DAG.getBitcast(
DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV, MVT::v2i64, DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
DAG.getConstant(EltBits, DL, MVT::i8), DAG.getConstant(EltBits, DL, MVT::i8),
DAG.getConstant(LoIdx, DL, MVT::i8))); DAG.getConstant(LoIdx, DL, MVT::i8)));
if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) || if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
!SafeOffset(Offset + 1)) !SafeOffset(Offset + 1))
return DAG.getNode(ISD::BITCAST, DL, VT, Lo); return DAG.getBitcast(VT, Lo);
int HiIdx = (Offset + 1) * EltBits; int HiIdx = (Offset + 1) * EltBits;
SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, SDValue Hi = DAG.getBitcast(
DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV, MVT::v2i64, DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
DAG.getConstant(EltBits, DL, MVT::i8), DAG.getConstant(EltBits, DL, MVT::i8),
DAG.getConstant(HiIdx, DL, MVT::i8))); DAG.getConstant(HiIdx, DL, MVT::i8)));
return DAG.getNode(ISD::BITCAST, DL, VT, return DAG.getBitcast(VT,
DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi)); DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
} }
// If this would require more than 2 unpack instructions to expand, use // If this would require more than 2 unpack instructions to expand, use
@ -8180,7 +8180,7 @@ static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
// FIXME: Add support for scalar truncation where possible. // FIXME: Add support for scalar truncation where possible.
SDValue S = V.getOperand(Idx); SDValue S = V.getOperand(Idx);
if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits()) if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S); return DAG.getBitcast(EltVT, S);
} }
return SDValue(); return SDValue();
@ -27846,7 +27846,7 @@ combineVectorTruncationWithPACKUS(SDNode *N, SelectionDAG &DAG,
for (unsigned j = 1, e = InSVT.getSizeInBits() / OutSVT.getSizeInBits(); for (unsigned j = 1, e = InSVT.getSizeInBits() / OutSVT.getSizeInBits();
j < e; j *= 2, RegNum /= 2) { j < e; j *= 2, RegNum /= 2) {
for (unsigned i = 0; i < RegNum; i++) for (unsigned i = 0; i < RegNum; i++)
Regs[i] = DAG.getNode(ISD::BITCAST, DL, UnpackedVT, Regs[i]); Regs[i] = DAG.getBitcast(UnpackedVT, Regs[i]);
for (unsigned i = 0; i < RegNum / 2; i++) for (unsigned i = 0; i < RegNum / 2; i++)
Regs[i] = DAG.getNode(X86ISD::PACKUS, DL, PackedVT, Regs[i * 2], Regs[i] = DAG.getNode(X86ISD::PACKUS, DL, PackedVT, Regs[i * 2],
Regs[i * 2 + 1]); Regs[i * 2 + 1]);
@ -28026,8 +28026,8 @@ static SDValue lowerX86FPLogicOp(SDNode *N, SelectionDAG &DAG,
MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits()); MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements()); MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0)); SDValue Op0 = DAG.getBitcast(IntVT, N->getOperand(0));
SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1)); SDValue Op1 = DAG.getBitcast(IntVT, N->getOperand(1));
unsigned IntOpcode = 0; unsigned IntOpcode = 0;
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: llvm_unreachable("Unexpected FP logic op"); default: llvm_unreachable("Unexpected FP logic op");
@ -28037,7 +28037,7 @@ static SDValue lowerX86FPLogicOp(SDNode *N, SelectionDAG &DAG,
case X86ISD::FANDN: IntOpcode = X86ISD::ANDNP; break; case X86ISD::FANDN: IntOpcode = X86ISD::ANDNP; break;
} }
SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1); SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
return DAG.getNode(ISD::BITCAST, dl, VT, IntOp); return DAG.getBitcast(VT, IntOp);
} }
return SDValue(); return SDValue();
} }
@ -28194,7 +28194,7 @@ static SDValue combineVZextMovl(SDNode *N, SelectionDAG &DAG) {
if (Op.getOpcode() == X86ISD::VZEXT_LOAD && if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
VT.getVectorElementType().getSizeInBits() == VT.getVectorElementType().getSizeInBits() ==
OpVT.getVectorElementType().getSizeInBits()) { OpVT.getVectorElementType().getSizeInBits()) {
return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op); return DAG.getBitcast(VT, Op);
} }
return SDValue(); return SDValue();
} }