Allow physregs to occur in the dag with multiple types. Though I don't like
this, it is a requirement on PPC, which can have an f32 value in r3 at one point in a function and a f64 value in r3 at another point. :( llvm-svn: 23160
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@ -355,7 +355,7 @@ private:
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std::map<std::pair<unsigned, std::pair<SDOperand, SDOperand> >,
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SDNode *> BinaryOps;
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std::vector<RegisterSDNode*> RegNodes;
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std::map<std::pair<unsigned, MVT::ValueType>, RegisterSDNode*> RegNodes;
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std::vector<CondCodeSDNode*> CondCodeNodes;
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std::map<std::pair<SDOperand, std::pair<SDOperand, MVT::ValueType> >,
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