replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

[Hexagon] Update more testcases 

llvm-svn: 326830
This commit is contained in:
Krzysztof Parzyszek 2018-03-06 19:15:58 +00:00
parent c9f797fdd0
commit 18484de34b
34 changed files with 103 additions and 112 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/test/CodeGen/Hexagon/addr-calc-opt.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; RUN: llc -march=hexagon < %s | FileCheck %s
;
; Test whether we can produce minimal code for this complex address
; calculation.

2
llvm/test/CodeGen/Hexagon/adjust-latency-stackST.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -disable-post-ra < %s | FileCheck %s
; RUN: llc -march=hexagon < %s | FileCheck %s
; Make sure that if there's only one store to the stack, it gets packetized
; with allocframe as there's a latency of 2 cycles between allocframe and

6
llvm/test/CodeGen/Hexagon/args.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: r5:4 = combine(#6,#5)
; CHECK: r3:2 = combine(#4,#3)
; CHECK: r1:0 = combine(#2,#1)
; CHECK-DAG: r5:4 = combine(#6,#5)
; CHECK-DAG: r3:2 = combine(#4,#3)
; CHECK-DAG: r1:0 = combine(#2,#1)
; CHECK: memw(r29+#0) = #7

10
llvm/test/CodeGen/Hexagon/barrier-flag.ll
View File

@ -1,8 +1,7 @@
; RUN: llc -O2 < %s
; RUN: llc -march=hexagon -O2 < %s
; Check for successful compilation. It originally caused an abort due to
; the "isBarrier" flag set on instructions that were not meant to have it.
target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
target triple = "hexagon"
; Function Attrs: nounwind optsize readnone
@ -114,12 +113,9 @@ for.end50: ; preds = %for.inc48
ret void
}
attributes #0 = { nounwind optsize readnone "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #0 = { nounwind optsize readnone }
attributes #1 = { nounwind optsize }
!llvm.ident = !{!0}
!0 = !{!"Clang 3.1"}
!1 = !{!2, !2, i64 0}
!2 = !{!"omnipotent char", !3, i64 0}
!3 = !{!"Simple C/C++ TBAA"}

2
llvm/test/CodeGen/Hexagon/base-offset-post.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s
; RUN: llc -march=hexagon < %s
; REQUIRES: asserts
; Test that the accessSize is set on a post-increment store. If not, an assert

2
llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll
View File

@ -30,4 +30,4 @@ b9: ; preds = %b6, %b4
ret i32 %v10
}
attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" "target-features"="-hvxv60,-long-calls" }
attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }

3
llvm/test/CodeGen/Hexagon/bit-eval.ll
View File

@ -1,6 +1,5 @@
; RUN: llc < %s | FileCheck %s
; RUN: llc -march=hexagon < %s | FileCheck %s
target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
target triple = "hexagon"
; CHECK-LABEL: test1:

2
llvm/test/CodeGen/Hexagon/bitconvert-vector.ll
View File

@ -24,4 +24,4 @@ entry:
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }

2
llvm/test/CodeGen/Hexagon/block-addr.ll
View File

@ -60,4 +60,4 @@ label6:
br label %while.body
}
attributes #0 = { noreturn nounwind "target-cpu"="hexagonv4" }
attributes #0 = { noreturn nounwind }

2
llvm/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll
View File

@ -3,7 +3,7 @@
; Check that the testcase compiles successfully. Expect that if-conversion
; took place.
; CHECK-LABEL: fred:
; CHECK: if (!p0) r1 = memw(r0+#0)
; CHECK: if (!p0) r{{[0-9]+}} = memw(r{{[0-9]+}}+#0)
target triple = "hexagon"

2
llvm/test/CodeGen/Hexagon/builtin-expect.ll
View File

@ -39,6 +39,6 @@ b14: ; preds = %b13, %b10
declare i32 @bar(i32) local_unnamed_addr #0
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b,-long-calls" }
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b,-long-calls" }
!0 = !{!"branch_weights", i32 1, i32 2000}

11
llvm/test/CodeGen/Hexagon/calling-conv-2.ll
View File

@ -1,13 +1,14 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 <%s | \
; RUN: FileCheck %s --check-prefix=CHECK-ONE
; RUN: llc -march=hexagon < %s | FileCheck %s
%struct.test_struct = type { i32, i8, i64 }
; CHECK-ONE: r1 = #45
; CHECK: r1 = #45
define void @foo(%struct.test_struct* noalias nocapture sret %agg.result, i32 %a) #0 {
entry:
call void @bar(%struct.test_struct* sret %agg.result, i32 45) #2
call void @bar(%struct.test_struct* sret %agg.result, i32 45) #0
ret void
}
declare void @bar(%struct.test_struct* sret, i32) #1
declare void @bar(%struct.test_struct* sret, i32) #0
attributes #0 = { nounwind }

4
llvm/test/CodeGen/Hexagon/callr-dep-edge.ll
View File

@ -5,9 +5,9 @@ target triple = "hexagon"
@fp = common global i32 (...)* null, align 4
; CHECK: r0 = memw
; CHECK: [[REG:r[0-9]+]] = memw
; CHECK: {
; CHECK: callr r0
; CHECK: callr [[REG]]
; Function Attrs: nounwind
define i32 @foo() #0 {

8
llvm/test/CodeGen/Hexagon/cext-valid-packet2.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -mcpu=hexagonv55 < %s | FileCheck %s
; Check that the packetizer generates valid packets with constant
; extended add and base+offset store instructions.
@ -6,6 +6,12 @@
; CHECK-NEXT: memw(r{{[0-9]+}}+##12000) = r{{[0-9]+}}.new
; CHECK-NEXT: }
; RUN: llc -march=hexagon -mcpu=hexagonv60 < %s | FileCheck %s -check-prefix=CHECK-NEW
; Check that the packetizer generates .new store for v60 which has BSB scheduling model.
; CHECK-NEW: [[REG0:r([0-9]+)]] = add(r{{[0-9]+}},##200000)
; CHECK-NEW: memw(r{{[0-9]+}}+##12000) = [[REG0]].new
define void @test(i32* nocapture %a, i32* nocapture %b, i32 %c) nounwind {
entry:
%0 = load i32, i32* %a, align 4

12
llvm/test/CodeGen/Hexagon/circ_ld.ll
View File

@ -26,7 +26,7 @@ entry:
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
%0 = bitcast i16* %arrayidx to i8*
%or = or i32 %shr1, 33554432
; CHECK: = memb(r{{[0-9]*}}++#-1:circ(m{{[0-1]}}))
; CHECK: = memb(r{{[0-9]+}}++#-1:circ(m{{[0-1]}}))
%1 = call i8* @llvm.hexagon.circ.ldb(i8* %0, i8* %inputLR, i32 %or, i32 -1)
%2 = load i8, i8* %inputLR, align 1, !tbaa !0
ret i8 %2
@ -45,7 +45,7 @@ entry:
%1 = bitcast i64* %inputLR to i8*
%shl = shl nuw nsw i32 %shr1, 3
%or = or i32 %shl, 83886080
; CHECK: = memd(r{{[0-9]*}}++#-8:circ(m{{[0-1]}}))
; CHECK: = memd(r{{[0-9]+}}++#-8:circ(m{{[0-1]}}))
%2 = call i8* @llvm.hexagon.circ.ldd(i8* %0, i8* %1, i32 %or, i32 -8)
%3 = bitcast i8* %1 to i64*
%4 = load i64, i64* %3, align 8, !tbaa !0
@ -64,7 +64,7 @@ entry:
%0 = bitcast i16* %arrayidx to i8*
%1 = bitcast i16* %inputLR to i8*
%or = or i32 %shr1, 50331648
; CHECK: = memh(r{{[0-9]*}}++#-2:circ(m{{[0-1]}}))
; CHECK: = memh(r{{[0-9]+}}++#-2:circ(m{{[0-1]}}))
%2 = call i8* @llvm.hexagon.circ.ldh(i8* %0, i8* %1, i32 %or, i32 -2)
%3 = bitcast i8* %1 to i16*
%4 = load i16, i16* %3, align 2, !tbaa !2
@ -82,7 +82,7 @@ entry:
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
%0 = bitcast i16* %arrayidx to i8*
%or = or i32 %shr1, 33554432
; CHECK: = memub(r{{[0-9]*}}++#-1:circ(m{{[0-1]}}))
; CHECK: = memub(r{{[0-9]+}}++#-1:circ(m{{[0-1]}}))
%1 = call i8* @llvm.hexagon.circ.ldub(i8* %0, i8* %inputLR, i32 %or, i32 -1)
%2 = load i8, i8* %inputLR, align 1, !tbaa !0
ret i8 %2
@ -100,7 +100,7 @@ entry:
%0 = bitcast i16* %arrayidx to i8*
%1 = bitcast i16* %inputLR to i8*
%or = or i32 %shr1, 50331648
; CHECK: = memuh(r{{[0-9]*}}++#-2:circ(m{{[0-1]}}))
; CHECK: = memuh(r{{[0-9]+}}++#-2:circ(m{{[0-1]}}))
%2 = call i8* @llvm.hexagon.circ.lduh(i8* %0, i8* %1, i32 %or, i32 -2)
%3 = bitcast i8* %1 to i16*
%4 = load i16, i16* %3, align 2, !tbaa !2
@ -120,7 +120,7 @@ entry:
%1 = bitcast i32* %inputLR to i8*
%shl = shl nuw nsw i32 %shr1, 2
%or = or i32 %shl, 67108864
; CHECK: = memw(r{{[0-9]*}}++#-4:circ(m{{[0-1]}}))
; CHECK: = memw(r{{[0-9]+}}++#-4:circ(m{{[0-1]}}))
%2 = call i8* @llvm.hexagon.circ.ldw(i8* %0, i8* %1, i32 %or, i32 -4)
%3 = bitcast i8* %1 to i32*
%4 = load i32, i32* %3, align 4, !tbaa !3

72
llvm/test/CodeGen/Hexagon/circ_ldd_bug.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -O2 < %s
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
; RUN: llc -march=hexagon -O2 < %s
target triple = "hexagon"
; We would fail on this file with:
@ -24,7 +24,7 @@ entry:
%idxprom = sext i16 %var2 to i32
%arrayidx = getelementptr inbounds i16, i16* %var1, i32 %idxprom
%0 = bitcast i16* %var3 to i64*
%1 = load i64, i64* %0, align 8, !tbaa !1
%1 = load i64, i64* %0, align 8
%2 = bitcast i16* %arrayidx to i8*
%3 = bitcast i64* %var4 to i8*
%shl = shl nuw nsw i32 %shr5, 3
@ -32,7 +32,7 @@ entry:
%4 = call i8* @llvm.hexagon.circ.ldd(i8* %2, i8* %3, i32 %or, i32 -8)
%sub = add nsw i32 %shr5, -1
%cmp6 = icmp sgt i32 %sub, 0
%5 = load i64, i64* %var4, align 8, !tbaa !1
%5 = load i64, i64* %var4, align 8
%6 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 0, i64 %1, i64 %5)
br i1 %cmp6, label %for.body.lr.ph, label %for.end
@ -72,11 +72,11 @@ unr.cmp: ; preds = %unr.cmp24
for.body.unr: ; preds = %unr.cmp
%11 = call i8* @llvm.hexagon.circ.ldd(i8* %4, i8* %3, i32 %or, i32 -8)
%12 = load i64, i64* %7, align 8, !tbaa !1
%12 = load i64, i64* %7, align 8
%inc.unr = add nsw i32 0, 1
%incdec.ptr4.unr = getelementptr inbounds i64, i64* %7, i32 1
%cmp.unr = icmp slt i32 %inc.unr, %sub
%13 = load i64, i64* %var4, align 8, !tbaa !1
%13 = load i64, i64* %var4, align 8
%14 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %6, i64 %12, i64 %13)
br label %for.body.unr13
@ -86,11 +86,11 @@ for.body.unr13: ; preds = %for.body.unr, %unr.
%var8.0.in8.unr = phi i8* [ %4, %unr.cmp ], [ %11, %for.body.unr ]
%i.07.unr = phi i32 [ 0, %unr.cmp ], [ %inc.unr, %for.body.unr ]
%16 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr, i8* %3, i32 %or, i32 -8)
%17 = load i64, i64* %pvar6.09.unr, align 8, !tbaa !1
%17 = load i64, i64* %pvar6.09.unr, align 8
%inc.unr14 = add nsw i32 %i.07.unr, 1
%incdec.ptr4.unr15 = getelementptr inbounds i64, i64* %pvar6.09.unr, i32 1
%cmp.unr16 = icmp slt i32 %inc.unr14, %sub
%18 = load i64, i64* %var4, align 8, !tbaa !1
%18 = load i64, i64* %var4, align 8
%19 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %15, i64 %17, i64 %18)
br label %for.body.unr17
@ -100,11 +100,11 @@ for.body.unr17: ; preds = %for.body.unr13, %un
%var8.0.in8.unr19 = phi i8* [ %4, %unr.cmp24 ], [ %16, %for.body.unr13 ]
%i.07.unr20 = phi i32 [ 0, %unr.cmp24 ], [ %inc.unr14, %for.body.unr13 ]
%21 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr19, i8* %3, i32 %or, i32 -8)
%22 = load i64, i64* %pvar6.09.unr18, align 8, !tbaa !1
%22 = load i64, i64* %pvar6.09.unr18, align 8
%inc.unr21 = add nsw i32 %i.07.unr20, 1
%incdec.ptr4.unr22 = getelementptr inbounds i64, i64* %pvar6.09.unr18, i32 1
%cmp.unr23 = icmp slt i32 %inc.unr21, %sub
%23 = load i64, i64* %var4, align 8, !tbaa !1
%23 = load i64, i64* %var4, align 8
%24 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %20, i64 %22, i64 %23)
br label %for.body.unr26
@ -114,11 +114,11 @@ for.body.unr26: ; preds = %for.body.unr17, %un
%var8.0.in8.unr28 = phi i8* [ %4, %unr.cmp33 ], [ %21, %for.body.unr17 ]
%i.07.unr29 = phi i32 [ 0, %unr.cmp33 ], [ %inc.unr21, %for.body.unr17 ]
%26 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr28, i8* %3, i32 %or, i32 -8)
%27 = load i64, i64* %pvar6.09.unr27, align 8, !tbaa !1
%27 = load i64, i64* %pvar6.09.unr27, align 8
%inc.unr30 = add nsw i32 %i.07.unr29, 1
%incdec.ptr4.unr31 = getelementptr inbounds i64, i64* %pvar6.09.unr27, i32 1
%cmp.unr32 = icmp slt i32 %inc.unr30, %sub
%28 = load i64, i64* %var4, align 8, !tbaa !1
%28 = load i64, i64* %var4, align 8
%29 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %25, i64 %27, i64 %28)
br label %for.body.unr35
@ -128,11 +128,11 @@ for.body.unr35: ; preds = %for.body.unr26, %un
%var8.0.in8.unr37 = phi i8* [ %4, %unr.cmp42 ], [ %26, %for.body.unr26 ]
%i.07.unr38 = phi i32 [ 0, %unr.cmp42 ], [ %inc.unr30, %for.body.unr26 ]
%31 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr37, i8* %3, i32 %or, i32 -8)
%32 = load i64, i64* %pvar6.09.unr36, align 8, !tbaa !1
%32 = load i64, i64* %pvar6.09.unr36, align 8
%inc.unr39 = add nsw i32 %i.07.unr38, 1
%incdec.ptr4.unr40 = getelementptr inbounds i64, i64* %pvar6.09.unr36, i32 1
%cmp.unr41 = icmp slt i32 %inc.unr39, %sub
%33 = load i64, i64* %var4, align 8, !tbaa !1
%33 = load i64, i64* %var4, align 8
%34 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %30, i64 %32, i64 %33)
br label %for.body.unr44
@ -142,11 +142,11 @@ for.body.unr44: ; preds = %for.body.unr35, %un
%var8.0.in8.unr46 = phi i8* [ %4, %unr.cmp51 ], [ %31, %for.body.unr35 ]
%i.07.unr47 = phi i32 [ 0, %unr.cmp51 ], [ %inc.unr39, %for.body.unr35 ]
%36 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr46, i8* %3, i32 %or, i32 -8)
%37 = load i64, i64* %pvar6.09.unr45, align 8, !tbaa !1
%37 = load i64, i64* %pvar6.09.unr45, align 8
%inc.unr48 = add nsw i32 %i.07.unr47, 1
%incdec.ptr4.unr49 = getelementptr inbounds i64, i64* %pvar6.09.unr45, i32 1
%cmp.unr50 = icmp slt i32 %inc.unr48, %sub
%38 = load i64, i64* %var4, align 8, !tbaa !1
%38 = load i64, i64* %var4, align 8
%39 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %35, i64 %37, i64 %38)
br label %for.body.unr53
@ -156,11 +156,11 @@ for.body.unr53: ; preds = %for.body.unr44, %un
%var8.0.in8.unr55 = phi i8* [ %4, %unr.cmp60 ], [ %36, %for.body.unr44 ]
%i.07.unr56 = phi i32 [ 0, %unr.cmp60 ], [ %inc.unr48, %for.body.unr44 ]
%41 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr55, i8* %3, i32 %or, i32 -8)
%42 = load i64, i64* %pvar6.09.unr54, align 8, !tbaa !1
%42 = load i64, i64* %pvar6.09.unr54, align 8
%inc.unr57 = add nsw i32 %i.07.unr56, 1
%incdec.ptr4.unr58 = getelementptr inbounds i64, i64* %pvar6.09.unr54, i32 1
%cmp.unr59 = icmp slt i32 %inc.unr57, %sub
%43 = load i64, i64* %var4, align 8, !tbaa !1
%43 = load i64, i64* %var4, align 8
%44 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %40, i64 %42, i64 %43)
br label %for.body.lr.ph.split
@ -182,51 +182,51 @@ for.body: ; preds = %for.body, %for.body
%var8.0.in8 = phi i8* [ %var8.0.in8.unr63, %for.body.lr.ph.split.split ], [ %75, %for.body ]
%i.07 = phi i32 [ %i.07.unr64, %for.body.lr.ph.split.split ], [ %inc.7, %for.body ]
%47 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8, i8* %3, i32 %or, i32 -8)
%48 = load i64, i64* %pvar6.09, align 8, !tbaa !1
%48 = load i64, i64* %pvar6.09, align 8
%inc = add nsw i32 %i.07, 1
%49 = load i64, i64* %var4, align 8, !tbaa !1
%49 = load i64, i64* %var4, align 8
%50 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %46, i64 %48, i64 %49)
%51 = call i8* @llvm.hexagon.circ.ldd(i8* %47, i8* %3, i32 %or, i32 -8)
%scevgep = getelementptr i64, i64* %pvar6.09, i32 1
%52 = load i64, i64* %scevgep, align 8, !tbaa !1
%52 = load i64, i64* %scevgep, align 8
%inc.1 = add nsw i32 %inc, 1
%53 = load i64, i64* %var4, align 8, !tbaa !1
%53 = load i64, i64* %var4, align 8
%54 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %50, i64 %52, i64 %53)
%55 = call i8* @llvm.hexagon.circ.ldd(i8* %51, i8* %3, i32 %or, i32 -8)
%scevgep65 = getelementptr i64, i64* %scevgep, i32 1
%56 = load i64, i64* %scevgep65, align 8, !tbaa !1
%56 = load i64, i64* %scevgep65, align 8
%inc.2 = add nsw i32 %inc.1, 1
%57 = load i64, i64* %var4, align 8, !tbaa !1
%57 = load i64, i64* %var4, align 8
%58 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %54, i64 %56, i64 %57)
%59 = call i8* @llvm.hexagon.circ.ldd(i8* %55, i8* %3, i32 %or, i32 -8)
%scevgep66 = getelementptr i64, i64* %scevgep65, i32 1
%60 = load i64, i64* %scevgep66, align 8, !tbaa !1
%60 = load i64, i64* %scevgep66, align 8
%inc.3 = add nsw i32 %inc.2, 1
%61 = load i64, i64* %var4, align 8, !tbaa !1
%61 = load i64, i64* %var4, align 8
%62 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %58, i64 %60, i64 %61)
%63 = call i8* @llvm.hexagon.circ.ldd(i8* %59, i8* %3, i32 %or, i32 -8)
%scevgep67 = getelementptr i64, i64* %scevgep66, i32 1
%64 = load i64, i64* %scevgep67, align 8, !tbaa !1
%64 = load i64, i64* %scevgep67, align 8
%inc.4 = add nsw i32 %inc.3, 1
%65 = load i64, i64* %var4, align 8, !tbaa !1
%65 = load i64, i64* %var4, align 8
%66 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %62, i64 %64, i64 %65)
%67 = call i8* @llvm.hexagon.circ.ldd(i8* %63, i8* %3, i32 %or, i32 -8)
%scevgep68 = getelementptr i64, i64* %scevgep67, i32 1
%68 = load i64, i64* %scevgep68, align 8, !tbaa !1
%68 = load i64, i64* %scevgep68, align 8
%inc.5 = add nsw i32 %inc.4, 1
%69 = load i64, i64* %var4, align 8, !tbaa !1
%69 = load i64, i64* %var4, align 8
%70 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %66, i64 %68, i64 %69)
%71 = call i8* @llvm.hexagon.circ.ldd(i8* %67, i8* %3, i32 %or, i32 -8)
%scevgep69 = getelementptr i64, i64* %scevgep68, i32 1
%72 = load i64, i64* %scevgep69, align 8, !tbaa !1
%72 = load i64, i64* %scevgep69, align 8
%inc.6 = add nsw i32 %inc.5, 1
%73 = load i64, i64* %var4, align 8, !tbaa !1
%73 = load i64, i64* %var4, align 8
%74 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %70, i64 %72, i64 %73)
%75 = call i8* @llvm.hexagon.circ.ldd(i8* %71, i8* %3, i32 %or, i32 -8)
%scevgep70 = getelementptr i64, i64* %scevgep69, i32 1
%76 = load i64, i64* %scevgep70, align 8, !tbaa !1
%76 = load i64, i64* %scevgep70, align 8
%inc.7 = add nsw i32 %inc.6, 1
%77 = load i64, i64* %var4, align 8, !tbaa !1
%77 = load i64, i64* %var4, align 8
%78 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %74, i64 %76, i64 %77)
%cmp.7 = icmp slt i32 %inc.7, %sub
%scevgep71 = getelementptr i64, i64* %scevgep70, i32 1
@ -249,7 +249,3 @@ for.end: ; preds = %for.end.loopexit, %
declare i64 @llvm.hexagon.M2.vdmacs.s1(i64, i64, i64) nounwind readnone
declare i32 @llvm.hexagon.S2.vrndpackwhs(i64) nounwind readnone
!0 = !{!"long long", !1}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}

2
llvm/test/CodeGen/Hexagon/circ_ldw.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; CHECK: r{{[0-9]*}} = memw(r{{[0-9]*}}++#-4:circ(m0))
; CHECK: r{{[0-9]*}} = memw(r{{[0-9]+}}++#-4:circ(m0))
%union.vect64 = type { i64 }

10
llvm/test/CodeGen/Hexagon/circ_st.ll
View File

@ -23,7 +23,7 @@ entry:
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
%0 = bitcast i16* %arrayidx to i8*
%or = or i32 %shr2, 33554432
; CHECK: memb(r{{[0-9]*}}++#-1:circ(m{{[0-1]}}))
; CHECK: memb(r{{[0-9]+}}++#-1:circ(m{{[0-1]}}))
%1 = tail call i8* @llvm.hexagon.circ.stb(i8* %0, i32 0, i32 %or, i32 -1)
ret i8 0
}
@ -39,7 +39,7 @@ entry:
%0 = bitcast i16* %arrayidx to i8*
%shl = shl nuw nsw i32 %shr1, 3
%or = or i32 %shl, 83886080
; CHECK: memd(r{{[0-9]*}}++#-8:circ(m{{[0-1]}}))
; CHECK: memd(r{{[0-9]+}}++#-8:circ(m{{[0-1]}}))
%1 = tail call i8* @llvm.hexagon.circ.std(i8* %0, i64 undef, i32 %or, i32 -8)
ret i64 0
}
@ -54,7 +54,7 @@ entry:
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
%0 = bitcast i16* %arrayidx to i8*
%or = or i32 %shr2, 50331648
; CHECK: memh(r{{[0-9]*}}++#-2:circ(m{{[0-1]}}))
; CHECK: memh(r{{[0-9]+}}++#-2:circ(m{{[0-1]}}))
%1 = tail call i8* @llvm.hexagon.circ.sth(i8* %0, i32 0, i32 %or, i32 -2)
ret i16 0
}
@ -69,7 +69,7 @@ entry:
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
%0 = bitcast i16* %arrayidx to i8*
%or = or i32 %shr2, 50331648
; CHECK: memh(r{{[0-9]*}}++#-2:circ(m{{[0-1]}})) = r{{[0-9]*}}.h
; CHECK: memh(r{{[0-9]+}}++#-2:circ(m{{[0-1]}})) = r{{[0-9]*}}.h
%1 = tail call i8* @llvm.hexagon.circ.sthhi(i8* %0, i32 0, i32 %or, i32 -2)
ret i16 0
}
@ -85,7 +85,7 @@ entry:
%0 = bitcast i16* %arrayidx to i8*
%shl = shl nuw nsw i32 %shr1, 2
%or = or i32 %shl, 67108864
; CHECK: memw(r{{[0-9]*}}++#-4:circ(m{{[0-1]}}))
; CHECK: memw(r{{[0-9]+}}++#-4:circ(m{{[0-1]}}))
%1 = tail call i8* @llvm.hexagon.circ.stw(i8* %0, i32 undef, i32 %or, i32 -4)
ret i32 0
}

2
llvm/test/CodeGen/Hexagon/clr_set_toggle.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-bit=0 < %s | FileCheck %s
; RUN: llc -march=hexagon -hexagon-bit=0 < %s | FileCheck %s
; Optimized bitwise operations.
define i32 @my_clrbit(i32 %x) nounwind {

2
llvm/test/CodeGen/Hexagon/cmp-extend.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; RUN: llc -march=hexagon < %s | FileCheck %s
%struct.RESULTS_S.A = type { i16, i16, i16, [4 x i8*], i32, i32, i32, %struct.list_head_s.B*, %struct.MAT_PARAMS_S.D, i16, i16, i16, i16, i16, %struct.CORE_PORTABLE_S.E }
%struct.list_head_s.B = type { %struct.list_head_s.B*, %struct.list_data_s.C* }

2
llvm/test/CodeGen/Hexagon/cmp_pred2.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; RUN: llc -march=hexagon < %s | FileCheck %s
; Make sure that the assembler mapped compare instructions are correctly generated.
@c = common global i32 0, align 4

2
llvm/test/CodeGen/Hexagon/cmpb-eq.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK-NOT: cmpb.eq(r{{[0-9]+}}, #-1)
; CHECK-NOT: cmpb.eq(r{{[0-9]+}},#-1)
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
target triple = "hexagon"

2
llvm/test/CodeGen/Hexagon/combine.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr -hexagon-bit=0 < %s | FileCheck %s
; RUN: llc -march=hexagon -disable-hsdr -hexagon-bit=0 < %s | FileCheck %s
; CHECK: combine(r{{[0-9]+}},r{{[0-9]+}})
@j = external global i32

2
llvm/test/CodeGen/Hexagon/combine_ir.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-hsdr < %s | FileCheck %s
; RUN: llc -march=hexagon -disable-hsdr < %s | FileCheck %s
declare void @bar(i64)

2
llvm/test/CodeGen/Hexagon/common-gep-basic.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: mpyi
; CHECK-NOT: mpyi
; The mpyis from the two GEPs should be commoned out.

10
llvm/test/CodeGen/Hexagon/constp-clb.ll
View File

@ -1,7 +1,6 @@
; RUN: llc -mcpu=hexagonv5 < %s
; RUN: llc -march=hexagon < %s
; REQUIRES: asserts
target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
target triple = "hexagon-unknown--elf"
; Function Attrs: nounwind readnone
@ -13,11 +12,10 @@ entry:
}
; Function Attrs: nounwind readnone
declare i32 @llvm.hexagon.S2.clbp(i64) #1
declare i32 @llvm.hexagon.S2.clbp(i64) #0
; Function Attrs: nounwind readnone
declare i64 @llvm.hexagon.A4.combineir(i32, i32) #1
declare i64 @llvm.hexagon.A4.combineir(i32, i32) #0
attributes #0 = { nounwind readnone "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
attributes #0 = { nounwind readnone }

3
llvm/test/CodeGen/Hexagon/constp-ctb.ll
View File

@ -1,7 +1,6 @@
; RUN: llc < %s
; RUN: llc -march=hexagon < %s
; REQUIRES: asserts
target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
target triple = "hexagon-unknown--elf"
; Function Attrs: nounwind readnone

2
llvm/test/CodeGen/Hexagon/constp-rewrite-branches.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -O2 -march hexagon < %s | FileCheck %s
; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
define i32 @foo(i32 %x) {
%p = icmp eq i32 %x, 0

3
llvm/test/CodeGen/Hexagon/constp-vsplat.ll
View File

@ -1,6 +1,5 @@
; RUN: llc < %s
; RUN: llc -march=hexagon < %s
; REQUIRES: asserts
target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
target triple = "hexagon"
; Function Attrs: nounwind readnone

2
llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll
View File

@ -14,4 +14,4 @@ entry:
declare <32 x i32> @llvm.hexagon.V6.vrdelta.128B(<32 x i32>, <32 x i32>)
declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1>, <32 x i32>, <32 x i32>)
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }

2
llvm/test/CodeGen/Hexagon/dead-store-stack.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -O2 -march=hexagon -mcpu=hexagonv62< %s | FileCheck %s
; RUN: llc -O2 -march=hexagon -mcpu=hexagonv62 < %s | FileCheck %s
; CHECK: ParseFunc:
; CHECK: r[[ARG0:[0-9]+]] = memuh(r[[ARG1:[0-9]+]]+#[[OFFSET:[0-9]+]])
; CHECK: memw(r[[ARG1]]+#[[OFFSET]]) = r[[ARG0]]

7
llvm/test/CodeGen/Hexagon/early-if-spare.ll
View File

@ -1,13 +1,12 @@
; RUN: llc -O2 -mcpu=hexagonv5 < %s | FileCheck %s
; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
; Check if the three stores in the loop were predicated.
; CHECK: if{{.*}}memw
; CHECK: if{{.*}}memw
; CHECK: if{{.*}}memw
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
target triple = "hexagon"
define void @fred(i32 %n, i32* %bp) nounwind {
define void @fred(i32 %n, i32* %bp) #0 {
entry:
%cmp16 = icmp eq i32 %n, 0
br i1 %cmp16, label %for.end, label %for.body.lr.ph
@ -52,6 +51,8 @@ declare i32 @foo(i32*) nounwind
declare i32 @bar(i32*) nounwind
attributes #0 = { nounwind "target-cpu"="hexagonv5" }
!0 = !{!"int", !1}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}

6
llvm/test/CodeGen/Hexagon/early-if.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -O2 -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
; Rely on the comments generated by llc. Check that "if.then" was predicated.
; CHECK: while.body13
; CHECK: if{{.*}}memd
@ -21,7 +21,7 @@ declare i64 @llvm.hexagon.A2.vaddws(i64, i64) nounwind readnone
declare i64 @llvm.hexagon.A2.vsubws(i64, i64) nounwind readnone
declare i32 @llvm.hexagon.A4.modwrapu(i32, i32) nounwind readnone
define void @foo(i32 %n, i64* %ptr) nounwind {
define void @foo(i32 %n, i64* %ptr) #0 {
entry:
br label %while.body
@ -73,3 +73,5 @@ end:
store i64 %10, i64* @A2, align 8
ret void
}
attributes #0 = { nounwind "target-cpu"="hexagonv5" }

12
llvm/test/CodeGen/Hexagon/expand-condsets-rm-segment.ll
View File

@ -1,7 +1,6 @@
; RUN: llc -O2 < %s
; RUN: llc -march=hexagon -O2 < %s
; REQUIRES: asserts
target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
target triple = "hexagon-unknown--elf"
%struct.cpumask = type { [1 x i32] }
@ -106,15 +105,10 @@ if.end43: ; preds = %if.else37, %if.then
}
declare i32 @get_update_sysctl_factor() #0
declare i32 @__bitmap_weight(i32*, i32) #1
declare i32 @__bitmap_weight(i32*, i32) #0
attributes #0 = { noinline nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { nounwind }
attributes #0 = { noinline nounwind }
!llvm.ident = !{!0}
!0 = !{!"Clang 3.1"}
!1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0}