replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Adds support for the Cortex-A17 to the ARM backend 

Patch by Matthew Wahab.

llvm-svn: 219606
This commit is contained in:
Renato Golin 2014-10-13 10:22:19 +00:00
parent 642daf0c0c
commit 16ea8ba3bc
3 changed files with 48 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
llvm/lib/Target/ARM/ARM.td
View File

@ -228,6 +228,15 @@ def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
FeatureAvoidPartialCPSR, FeatureAvoidPartialCPSR,
FeatureTrustZone, FeatureVirtualization]>; FeatureTrustZone, FeatureVirtualization]>;
def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
"Cortex-A17 ARM processors",
[FeatureVMLxForwarding,
FeatureT2XtPk, FeatureVFP4,
FeatureHWDiv, FeatureHWDivARM,
FeatureAvoidPartialCPSR,
FeatureVirtualization,
FeatureTrustZone]>;
def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
"Cortex-A53 ARM processors", "Cortex-A53 ARM processors",
[FeatureHWDiv, FeatureHWDivARM, [FeatureHWDiv, FeatureHWDivARM,
@ -366,6 +375,12 @@ def : ProcessorModel<"cortex-a15", CortexA9Model,
FeatureDSPThumb2, FeatureHasRAS, FeatureDSPThumb2, FeatureHasRAS,
FeatureAClass]>; FeatureAClass]>;
// FIXME: A17 has currently the same Schedule model as A9
def : ProcessorModel<"cortex-a17", CortexA9Model,
[ProcA17, HasV7Ops, FeatureNEON, FeatureDB,
FeatureDSPThumb2, FeatureMP,
FeatureHasRAS, FeatureAClass]>;
// FIXME: krait has currently the same Schedule model as A9 // FIXME: krait has currently the same Schedule model as A9
def : ProcessorModel<"krait", CortexA9Model, def : ProcessorModel<"krait", CortexA9Model,
[ProcKrait, HasV7Ops, [ProcKrait, HasV7Ops,

2
llvm/lib/Target/ARM/ARMSubtarget.h
View File

@ -42,7 +42,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
protected: protected:
enum ARMProcFamilyEnum { enum ARMProcFamilyEnum {
Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15, Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
CortexR5, Swift, CortexA53, CortexA57, Krait CortexA17, CortexR5, Swift, CortexA53, CortexA57, Krait,
}; };
enum ARMProcClassEnum { enum ARMProcClassEnum {
None, AClass, RClass, MClass None, AClass, RClass, MClass

32
llvm/test/CodeGen/ARM/build-attributes.ll
View File

@ -22,6 +22,8 @@
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A12-NOFPU ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A12-NOFPU
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9-mp | FileCheck %s --check-prefix=CORTEX-A9-MP ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9-mp | FileCheck %s --check-prefix=CORTEX-A9-MP
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 | FileCheck %s --check-prefix=CORTEX-A15 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 | FileCheck %s --check-prefix=CORTEX-A15
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 | FileCheck %s --check-prefix=CORTEX-A17-DEFAULT
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A17-NOFPU
; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0
; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=CORTEX-M3 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=CORTEX-M3
; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT
@ -375,6 +377,36 @@
; CORTEX-A15: .eabi_attribute 44, 2 ; CORTEX-A15: .eabi_attribute 44, 2
; CORTEX-A15: .eabi_attribute 68, 3 ; CORTEX-A15: .eabi_attribute 68, 3
; CORTEX-A17-DEFAULT: .cpu cortex-a17
; CORTEX-A17-DEFAULT: .eabi_attribute 6, 10
; CORTEX-A17-DEFAULT: .eabi_attribute 7, 65
; CORTEX-A17-DEFAULT: .eabi_attribute 8, 1
; CORTEX-A17-DEFAULT: .eabi_attribute 9, 2
; CORTEX-A17-DEFAULT: .fpu neon-vfpv4
; CORTEX-A17-DEFAULT: .eabi_attribute 20, 1
; CORTEX-A17-DEFAULT: .eabi_attribute 21, 1
; CORTEX-A17-DEFAULT: .eabi_attribute 23, 3
; CORTEX-A17-DEFAULT: .eabi_attribute 24, 1
; CORTEX-A17-DEFAULT: .eabi_attribute 25, 1
; CORTEX-A17-DEFAULT: .eabi_attribute 42, 1
; CORTEX-A17-DEFAULT: .eabi_attribute 44, 2
; CORTEX-A17-DEFAULT: .eabi_attribute 68, 3
; CORTEX-A17-NOFPU: .cpu cortex-a17
; CORTEX-A17-NOFPU: .eabi_attribute 6, 10
; CORTEX-A17-NOFPU: .eabi_attribute 7, 65
; CORTEX-A17-NOFPU: .eabi_attribute 8, 1
; CORTEX-A17-NOFPU: .eabi_attribute 9, 2
; CORTEX-A17-NOFPU-NOT: .fpu
; CORTEX-A17-NOFPU: .eabi_attribute 20, 1
; CORTEX-A17-NOFPU: .eabi_attribute 21, 1
; CORTEX-A17-NOFPU: .eabi_attribute 23, 3
; CORTEX-A17-NOFPU: .eabi_attribute 24, 1
; CORTEX-A17-NOFPU: .eabi_attribute 25, 1
; CORTEX-A17-NOFPU: .eabi_attribute 42, 1
; CORTEX-A17-NOFPU: .eabi_attribute 44, 2
; CORTEX-A17-NOFPU: .eabi_attribute 68, 3
; CORTEX-M0: .cpu cortex-m0 ; CORTEX-M0: .cpu cortex-m0
; CORTEX-M0: .eabi_attribute 6, 12 ; CORTEX-M0: .eabi_attribute 6, 12
; CORTEX-M0-NOT: .eabi_attribute 7 ; CORTEX-M0-NOT: .eabi_attribute 7