diff --git a/llvm/include/llvm/Target/TargetInstrInfo.h b/llvm/include/llvm/Target/TargetInstrInfo.h index 8717d7208012..db3b813d70a9 100644 --- a/llvm/include/llvm/Target/TargetInstrInfo.h +++ b/llvm/include/llvm/Target/TargetInstrInfo.h @@ -52,37 +52,34 @@ const unsigned M_DELAY_SLOT_FLAG = 1 << 4; const unsigned M_LOAD_FLAG = 1 << 5; const unsigned M_STORE_FLAG = 1 << 6; -// M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones. -const unsigned M_2_ADDR_FLAG = 1 << 7; - -// M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be +// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be // changed into a 3-address instruction if the first two operands cannot be // assigned to the same register. The target must implement the // TargetInstrInfo::convertToThreeAddress method for this instruction. -const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 8; +const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7; // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, // Z), which produces the same result if Y and Z are exchanged. -const unsigned M_COMMUTABLE = 1 << 9; +const unsigned M_COMMUTABLE = 1 << 8; // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic // block? Typically this is things like return and branch instructions. // Various passes use this to insert code into the bottom of a basic block, but // before control flow occurs. -const unsigned M_TERMINATOR_FLAG = 1 << 10; +const unsigned M_TERMINATOR_FLAG = 1 << 9; // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom // insertion support when the DAG scheduler is inserting it into a machine basic // block. -const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 11; +const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10; // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra // operands in addition to the minimum number operands specified. -const unsigned M_VARIABLE_OPS = 1 << 12; +const unsigned M_VARIABLE_OPS = 1 << 11; // M_PREDICATED - Set if this instruction has a predicate that controls its // execution. -const unsigned M_PREDICATED = 1 << 13; +const unsigned M_PREDICATED = 1 << 12; // Machine operand flags @@ -184,9 +181,6 @@ public: return get(Opcode).Flags & M_RET_FLAG; } - bool isTwoAddrInstr(MachineOpCode Opcode) const { - return get(Opcode).Flags & M_2_ADDR_FLAG; - } bool isPredicated(MachineOpCode Opcode) const { return get(Opcode).Flags & M_PREDICATED; } diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index 50599c850de2..dbc50d6b1304 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -191,8 +191,6 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { mbbi->erase(mi); // Nuke the old inst. mi = New; ++NumConvertedTo3Addr; - assert(!TII.isTwoAddrInstr(New->getOpcode()) && - "convertToThreeAddress returned a 2-addr instruction??"); // Done with this instruction. break; } diff --git a/llvm/lib/Target/X86/X86CodeEmitter.cpp b/llvm/lib/Target/X86/X86CodeEmitter.cpp index 8d1e91285eff..80a285e7350c 100644 --- a/llvm/lib/Target/X86/X86CodeEmitter.cpp +++ b/llvm/lib/Target/X86/X86CodeEmitter.cpp @@ -470,7 +470,8 @@ unsigned Emitter::determineREX(const MachineInstr &MI) { REX |= 1 << 3; if (MI.getNumOperands()) { - bool isTwoAddr = (Desc.Flags & M_2_ADDR_FLAG) != 0; + bool isTwoAddr = II->getNumOperands(Opcode) > 1 && + II->getOperandConstraint(Opcode, 1, TargetInstrInfo::TIED_TO) != -1; // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. bool isTrunc8 = isX86_64TruncToByte(Opcode); @@ -607,7 +608,9 @@ void Emitter::emitInstruction(const MachineInstr &MI) { // If this is a two-address instruction, skip one of the register operands. unsigned CurOp = 0; - CurOp += (Desc.Flags & M_2_ADDR_FLAG) != 0; + if (II->getNumOperands(Opcode) > 1 && + II->getOperandConstraint(Opcode, 1, TargetInstrInfo::TIED_TO) != -1) + CurOp++; unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode); switch (Desc.TSFlags & X86II::FormMask) { diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index aa3ed3089d74..45eae67c9491 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -284,14 +284,15 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, const TableEntry *OpcodeTablePtr = NULL; unsigned OpcodeTableSize = 0; bool isTwoAddrFold = false; + bool isTwoAddr = TII.getNumOperands(MI->getOpcode()) > 1 && + TII.getOperandConstraint(MI->getOpcode(), 1,TargetInstrInfo::TIED_TO) != -1; // Folding a memory location into the two-address part of a two-address // instruction is different than folding it other places. It requires // replacing the *two* registers with the memory location. - if (MI->getNumOperands() >= 2 && MI->getOperand(0).isReg() && + if (isTwoAddr && MI->getNumOperands() >= 2 && MI->getOperand(0).isReg() && MI->getOperand(1).isReg() && i < 2 && - MI->getOperand(0).getReg() == MI->getOperand(1).getReg() && - TII.isTwoAddrInstr(MI->getOpcode())) { + MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { static const TableEntry OpcodeTable[] = { { X86::ADC32ri, X86::ADC32mi }, { X86::ADC32ri8, X86::ADC32mi8 }, diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp index 0c5c45520359..deee320c5d51 100644 --- a/llvm/utils/TableGen/InstrInfoEmitter.cpp +++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp @@ -232,7 +232,6 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, if (Inst.isCall) OS << "|M_CALL_FLAG"; if (Inst.isLoad) OS << "|M_LOAD_FLAG"; if (Inst.isStore || isStore) OS << "|M_STORE_FLAG"; - if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG"; if (Inst.isPredicated) OS << "|M_PREDICATED"; if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR"; if (Inst.isCommutable) OS << "|M_COMMUTABLE";