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[PowerPC] Reduce register pressure by not materializing a constant just for use as an index register for X-Form loads/stores. 

For this example:
float test (int *arr) {
    return arr[2];
}

We currently generate the following code:
  li r4, 8
  lxsiwax f0, r3, r4
  xscvsxdsp f1, f0

With this patch, we will now generate:
  addi r3, r3, 8
  lxsiwax f0, 0, r3
  xscvsxdsp f1, f0

Originally reported in: https://bugs.llvm.org/show_bug.cgi?id=27204
Differential Revision: https://reviews.llvm.org/D35027

llvm-svn: 307553
This commit is contained in:
Lei Huang 2017-07-10 16:44:45 +00:00
parent ae9d6db769
commit 168d14b143
5 changed files with 58 additions and 16 deletions
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13
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -2239,10 +2239,15 @@ bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
if (SelectAddressRegReg(N, Base, Index, DAG))
return true;
// If the operand is an addition, always emit this as [r+r], since this is
// better (for code size, and execution, as the memop does the add for free)
// than emitting an explicit add.
if (N.getOpcode() == ISD::ADD) {
// If the address is the result of an add, we will utilize the fact that the
// address calculation includes an implicit add. However, we can reduce
// register pressure if we do not materialize a constant just for use as the
// index register. We only get rid of the add if it is not an add of a
// value and a 16-bit signed constant and both have a single use.
int16_t imm = 0;
if (N.getOpcode() == ISD::ADD &&
(!isIntS16Immediate(N.getOperand(1), imm) ||
!N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
Base = N.getOperand(0);
Index = N.getOperand(1);
return true;

4
llvm/test/CodeGen/PowerPC/build-vector-tests.ll
View File

@ -1028,7 +1028,7 @@ entry:
; P9LE: vperm
; P9LE: blr
; P8BE: sldi {{r[0-9]+}}, r4, 2
; P8BE-DAG: lxvw4x {{v[0-9]+}}, r3,
; P8BE-DAG: lxvw4x {{v[0-9]+}}, 0, r3
; P8BE-DAG: lxvw4x
; P8BE: vperm
; P8BE: blr
@ -2187,7 +2187,7 @@ entry:
; P9LE: vperm
; P9LE: blr
; P8BE-DAG: sldi {{r[0-9]+}}, r4, 2
; P8BE-DAG: lxvw4x {{v[0-9]+}}, r3
; P8BE-DAG: lxvw4x {{v[0-9]+}}, 0, r3
; P8BE-DAG: lxvw4x
; P8BE: vperm
; P8BE: blr

4
llvm/test/CodeGen/PowerPC/ppc64le-smallarg.ll
View File

@ -53,8 +53,8 @@ entry:
ret void
}
; CHECK: @caller2
; CHECK: li [[TOCOFF:[0-9]+]], 136
; CHECK: stxsspx {{[0-9]+}}, 1, [[TOCOFF]]
; CHECK: addi [[TOCOFF:[0-9]+]], {{[0-9]+}}, 136
; CHECK: stxsspx {{[0-9]+}}, 0, [[TOCOFF]]
; CHECK: bl test2
declare float @test2(float, float, float, float, float, float, float, float, float, float, float, float, float, float)

37
llvm/test/CodeGen/PowerPC/select-addrRegRegOnly.ll Normal file
View File

@ -0,0 +1,37 @@
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown -verify-machineinstrs < %s | FileCheck %s
; Function Attrs: norecurse nounwind readonly
define float @testSingleAccess(i32* nocapture readonly %arr) local_unnamed_addr #0 {
; CHECK-LABEL: testSingleAccess:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addi 3, 3, 8
; CHECK-NEXT: lxsiwax 0, 0, 3
; CHECK-NEXT: xscvsxdsp 1, 0
; CHECK-NEXT: blr
entry:
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 2
%0 = load i32, i32* %arrayidx, align 4
%conv = sitofp i32 %0 to float
ret float %conv
}
; Function Attrs: norecurse nounwind readonly
define float @testMultipleAccess(i32* nocapture readonly %arr) local_unnamed_addr #0 {
; CHECK-LABEL: testMultipleAccess:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: lwz 4, 8(3)
; CHECK-NEXT: lwz 12, 12(3)
; CHECK-NEXT: add 3, 12, 4
; CHECK-NEXT: mtvsrwa 0, 3
; CHECK-NEXT: xscvsxdsp 1, 0
; CHECK-NEXT: blr
entry:
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 2
%0 = load i32, i32* %arrayidx, align 4
%arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 3
%1 = load i32, i32* %arrayidx1, align 4
%add = add nsw i32 %1, %0
%conv = sitofp i32 %add to float
ret float %conv
}

16
llvm/test/CodeGen/PowerPC/vsx-partword-int-loads-and-stores.ll
View File

@ -321,8 +321,8 @@ entry:
; CHECK: lxsibzx 34, 0, 3
; CHECK-NEXT: vspltb 2, 2, 7
; CHECK-BE-LABEL: vecucus
; CHECK-BE: li [[OFFSET:[0-9]+]], 1
; CHECK-BE-NEXT: lxsibzx 34, 3, [[OFFSET]]
; CHECK-BE: addi [[OFFSET:[0-9]+]], [[OFFSET]], 1
; CHECK-BE-NEXT: lxsibzx 34, 0, [[OFFSET]]
; CHECK-BE-NEXT: vspltb 2, 2, 7
}
@ -385,8 +385,8 @@ entry:
; CHECK: lxsibzx 34, 0, 3
; CHECK-NEXT: vspltb 2, 2, 7
; CHECK-BE-LABEL: vecscus
; CHECK-BE: li [[OFFSET:[0-9]+]], 1
; CHECK-BE-NEXT: lxsibzx 34, 3, [[OFFSET]]
; CHECK-BE: addi [[OFFSET:[0-9]+]], [[OFFSET]], 1
; CHECK-BE-NEXT: lxsibzx 34, 0, [[OFFSET]]
; CHECK-BE-NEXT: vspltb 2, 2, 7
}
@ -487,8 +487,8 @@ entry:
; CHECK: lxsibzx 34, 0, 3
; CHECK-NEXT: vspltb 2, 2, 7
; CHECK-BE-LABEL: vecucss
; CHECK-BE: li [[OFFSET:[0-9]+]], 1
; CHECK-BE-NEXT: lxsibzx 34, 3, [[OFFSET]]
; CHECK-BE: addi [[OFFSET:[0-9]+]], [[OFFSET]], 1
; CHECK-BE-NEXT: lxsibzx 34, 0, [[OFFSET]]
; CHECK-BE-NEXT: vspltb 2, 2, 7
}
@ -540,8 +540,8 @@ entry:
; CHECK: lxsibzx 34, 0, 3
; CHECK-NEXT: vspltb 2, 2, 7
; CHECK-BE-LABEL: vecscss
; CHECK-BE: li [[OFFSET:[0-9]+]], 1
; CHECK-BE-NEXT: lxsibzx 34, 3, [[OFFSET]]
; CHECK-BE: addi [[OFFSET:[0-9]+]], [[OFFSET]], 1
; CHECK-BE-NEXT: lxsibzx 34, 0, [[OFFSET]]
; CHECK-BE-NEXT: vspltb 2, 2, 7
}