[RISCV] Add inline asm constraint A for RISC-V

This allows the constraint A to be used in inline asm for RISC-V, which
allows an address held in a register to be used.

This patch adds the minimal amount of code required to get operands with
the right constraints to compile.

Differential Revision: https://reviews.llvm.org/D54295

llvm-svn: 369093

clang/lib/Basic/Targets/RISCV.cpp

@@ -75,6 +75,10 @@ bool RISCVTargetInfo::validateAsmConstraint(
     // A floating-point register.
     Info.setAllowsRegister();
     return true;
+  case 'A':
+    // An address that is held in a general-purpose register.
+    Info.setAllowsMemory();
+    return true;
   }
 }
 

clang/test/CodeGen/riscv-inline-asm.c

@@ -38,3 +38,9 @@ void test_f() {
 // CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
   asm volatile ("" :: "f"(d));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}