[AMDGPU] Disassembler: Support for all VOP1 instructions.
Support all instructions with VOP1 encoding with 32 or 64-bit operands for VI subtarget: VGPR_32 and VReg_64 operand register classes VS_32 and VS_64 operand register classes with inline and literal constants Tests for VOP1 instructions. Patch by: skolton Reviewers: arsenm, tstellarAMD Review: http://reviews.llvm.org/D17194 llvm-svn: 261878
This commit is contained in:
Nikolay Haustov
parent
26df21d71e
commit
161a158e5c
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@ -39,67 +39,68 @@ typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
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static DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
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static DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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uint64_t Addr, const void *Decoder) {
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const AMDGPUDisassembler *Dis =
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const AMDGPUDisassembler *Dis =
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static_cast<const AMDGPUDisassembler *>(Decoder);
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static_cast<const AMDGPUDisassembler *>(Decoder);
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return Dis->DecodeVGPR_32RegisterClass(Inst, Imm, Addr);
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return Dis->DecodeVGPR_32RegisterClass(Inst, Imm, Addr);
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}
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}
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static DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
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static DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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uint64_t Addr, const void *Decoder) {
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const AMDGPUDisassembler *Dis =
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const AMDGPUDisassembler *Dis =
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static_cast<const AMDGPUDisassembler *>(Decoder);
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static_cast<const AMDGPUDisassembler *>(Decoder);
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return Dis->DecodeVS_32RegisterClass(Inst, Imm, Addr);
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return Dis->DecodeVS_32RegisterClass(Inst, Imm, Addr);
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}
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}
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static DecodeStatus DecodeVS_64RegisterClass(MCInst &Inst, unsigned Imm,
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static DecodeStatus DecodeVS_64RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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uint64_t Addr, const void *Decoder) {
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// ToDo
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const AMDGPUDisassembler *Dis =
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return MCDisassembler::Fail;
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static_cast<const AMDGPUDisassembler *>(Decoder);
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return Dis->DecodeVS_64RegisterClass(Inst, Imm, Addr);
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}
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}
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static DecodeStatus DecodeVReg_64RegisterClass(MCInst &Inst, unsigned Imm,
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static DecodeStatus DecodeVReg_64RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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const AMDGPUDisassembler *Dis =
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static_cast<const AMDGPUDisassembler *>(Decoder);
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return Dis->DecodeVReg_64RegisterClass(Inst, Imm, Addr);
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}
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static DecodeStatus DecodeVReg_96RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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uint64_t Addr, const void *Decoder) {
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// ToDo
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// ToDo
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return MCDisassembler::Fail;
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return MCDisassembler::Fail;
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}
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}
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static DecodeStatus DecodeVReg_96RegisterClass(MCInst &Inst, unsigned Imm,
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static DecodeStatus DecodeVReg_128RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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// ToDo
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return MCDisassembler::Fail;
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}
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static DecodeStatus DecodeVReg_128RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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uint64_t Addr, const void *Decoder) {
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// ToDo
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// ToDo
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return MCDisassembler::Fail;
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return MCDisassembler::Fail;
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}
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}
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static DecodeStatus DecodeSReg_32RegisterClass(MCInst &Inst, unsigned Imm,
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static DecodeStatus DecodeSReg_32RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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uint64_t Addr, const void *Decoder) {
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// ToDo
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// ToDo
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return MCDisassembler::Fail;
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return MCDisassembler::Fail;
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}
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}
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static DecodeStatus DecodeSReg_64RegisterClass(MCInst &Inst, unsigned Imm,
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static DecodeStatus DecodeSReg_64RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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uint64_t Addr, const void *Decoder) {
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// ToDo
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// ToDo
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return MCDisassembler::Fail;
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return MCDisassembler::Fail;
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}
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}
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static DecodeStatus DecodeSReg_128RegisterClass(MCInst &Inst, unsigned Imm,
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static DecodeStatus DecodeSReg_128RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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uint64_t Addr, const void *Decoder) {
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// ToDo
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// ToDo
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return MCDisassembler::Fail;
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return MCDisassembler::Fail;
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}
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}
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static DecodeStatus DecodeSReg_256RegisterClass(MCInst &Inst, unsigned Imm,
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static DecodeStatus DecodeSReg_256RegisterClass(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder) {
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uint64_t Addr, const void *Decoder) {
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// ToDo
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// ToDo
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return MCDisassembler::Fail;
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return MCDisassembler::Fail;
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}
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}
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#define GET_SUBTARGETINFO_ENUM
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#define GET_SUBTARGETINFO_ENUM
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#include "AMDGPUGenSubtargetInfo.inc"
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#include "AMDGPUGenSubtargetInfo.inc"
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#undef GET_SUBTARGETINFO_ENUM
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#undef GET_SUBTARGETINFO_ENUM
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@ -112,7 +113,7 @@ static DecodeStatus DecodeSReg_256RegisterClass(MCInst &Inst, unsigned Imm,
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DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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uint64_t Address,
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raw_ostream &WS,
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raw_ostream &WS,
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raw_ostream &CS) const {
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raw_ostream &CS) const {
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CommentStream = &CS;
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CommentStream = &CS;
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@ -120,6 +121,9 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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// ToDo: AMDGPUDisassembler supports only VI ISA.
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// ToDo: AMDGPUDisassembler supports only VI ISA.
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assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA.");
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assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA.");
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HasLiteral = false;
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this->Bytes = Bytes;
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// Try decode 32-bit instruction
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// Try decode 32-bit instruction
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if (Bytes.size() < 4) {
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if (Bytes.size() < 4) {
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Size = 0;
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Size = 0;
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@ -135,14 +139,19 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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Size = 0;
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Size = 0;
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return MCDisassembler::Fail;
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return MCDisassembler::Fail;
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}
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}
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Size = 4;
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if (HasLiteral == true) {
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Size = 8;
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HasLiteral = false;
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} else {
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Size = 4;
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}
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return MCDisassembler::Success;
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return MCDisassembler::Success;
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}
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}
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DecodeStatus AMDGPUDisassembler::DecodeLitFloat(unsigned Imm, uint32_t& F) const {
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DecodeStatus AMDGPUDisassembler::DecodeImmedFloat(unsigned Imm, uint32_t &F) const {
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// ToDo: case 248: 1/(2*PI) - is allowed only on VI
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// ToDo: case 248: 1/(2*PI) - is allowed only on VI
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// ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as
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// ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as
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// literal constant.
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// literal constant.
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switch(Imm) {
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switch(Imm) {
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case 240: F = FloatToBits(0.5f); return MCDisassembler::Success;
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case 240: F = FloatToBits(0.5f); return MCDisassembler::Success;
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@ -158,8 +167,23 @@ DecodeStatus AMDGPUDisassembler::DecodeLitFloat(unsigned Imm, uint32_t& F) const
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}
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}
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}
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}
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DecodeStatus AMDGPUDisassembler::DecodeLitInteger(unsigned Imm,
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DecodeStatus AMDGPUDisassembler::DecodeImmedDouble(unsigned Imm, uint64_t &D) const {
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int64_t& I) const {
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switch(Imm) {
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case 240: D = DoubleToBits(0.5); return MCDisassembler::Success;
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case 241: D = DoubleToBits(-0.5); return MCDisassembler::Success;
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case 242: D = DoubleToBits(1.0); return MCDisassembler::Success;
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case 243: D = DoubleToBits(-1.0); return MCDisassembler::Success;
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case 244: D = DoubleToBits(2.0); return MCDisassembler::Success;
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case 245: D = DoubleToBits(-2.0); return MCDisassembler::Success;
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case 246: D = DoubleToBits(4.0); return MCDisassembler::Success;
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case 247: D = DoubleToBits(-4.0); return MCDisassembler::Success;
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case 248: D = 0x3fc45f306dc9c882; return MCDisassembler::Success; // 1/(2*PI)
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default: return MCDisassembler::Fail;
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}
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}
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DecodeStatus AMDGPUDisassembler::DecodeImmedInteger(unsigned Imm,
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int64_t &I) const {
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if ((Imm >= 128) && (Imm <= 192)) {
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if ((Imm >= 128) && (Imm <= 192)) {
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I = Imm - 128;
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I = Imm - 128;
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return MCDisassembler::Success;
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return MCDisassembler::Success;
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@ -170,33 +194,91 @@ DecodeStatus AMDGPUDisassembler::DecodeLitInteger(unsigned Imm,
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return MCDisassembler::Fail;
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return MCDisassembler::Fail;
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}
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}
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DecodeStatus AMDGPUDisassembler::DecodeVgprRegister(unsigned Val,
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DecodeStatus AMDGPUDisassembler::DecodeVgprRegister(unsigned Val,
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unsigned& RegID) const {
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unsigned &RegID,
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if (Val > 255) {
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unsigned Size) const {
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if (Val > (256 - Size / 32)) {
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return MCDisassembler::Fail;
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return MCDisassembler::Fail;
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}
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}
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RegID = AMDGPUMCRegisterClasses[AMDGPU::VGPR_32RegClassID].getRegister(Val);
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unsigned RegClassID;
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switch (Size) {
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case 32: RegClassID = AMDGPU::VGPR_32RegClassID; break;
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case 64: RegClassID = AMDGPU::VReg_64RegClassID; break;
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case 96: RegClassID = AMDGPU::VReg_96RegClassID; break;
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case 128: RegClassID = AMDGPU::VReg_128RegClassID; break;
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case 256: RegClassID = AMDGPU::VReg_256RegClassID; break;
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case 512: RegClassID = AMDGPU::VReg_512RegClassID; break;
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default:
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return MCDisassembler::Fail;
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}
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RegID = AMDGPUMCRegisterClasses[RegClassID].getRegister(Val);
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return MCDisassembler::Success;
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return MCDisassembler::Success;
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}
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}
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DecodeStatus AMDGPUDisassembler::DecodeSgprRegister(unsigned Val,
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DecodeStatus AMDGPUDisassembler::DecodeSgprRegister(unsigned Val,
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unsigned& RegID) const {
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unsigned &RegID,
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unsigned Size) const {
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// ToDo: SI/CI have 104 SGPRs, VI - 102
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// ToDo: SI/CI have 104 SGPRs, VI - 102
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if (Val > 101) {
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unsigned RegClassID;
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switch (Size) {
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case 32:
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if (Val > 101) {
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return MCDisassembler::Fail;
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}
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RegClassID = AMDGPU::SGPR_32RegClassID;
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break;
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case 64:
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if ((Val % 2 != 0) || (Val > 100)) {
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return MCDisassembler::Fail;
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}
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Val /= 2;
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RegClassID = AMDGPU::SGPR_64RegClassID;
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break;
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case 128:
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// ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
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// this bundle?
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if ((Val % 4 != 0) || (Val > 96)) {
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return MCDisassembler::Fail;
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}
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Val /= 4;
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RegClassID = AMDGPU::SReg_128RegClassID;
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break;
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case 256:
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// ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
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// this bundle?
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if ((Val % 4 != 0) || (Val > 92)) {
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return MCDisassembler::Fail;
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}
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Val /= 4;
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RegClassID = AMDGPU::SReg_256RegClassID;
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break;
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case 512:
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// ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
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// this bundle?
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if ((Val % 4 != 0) || (Val > 84)) {
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return MCDisassembler::Fail;
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}
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Val /= 4;
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RegClassID = AMDGPU::SReg_512RegClassID;
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break;
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default:
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return MCDisassembler::Fail;
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return MCDisassembler::Fail;
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}
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}
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RegID = AMDGPUMCRegisterClasses[AMDGPU::SGPR_32RegClassID].getRegister(Val);
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RegID = AMDGPUMCRegisterClasses[RegClassID].getRegister(Val);
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return MCDisassembler::Success;
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return MCDisassembler::Success;
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}
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}
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DecodeStatus AMDGPUDisassembler::DecodeSrcRegister(unsigned Val,
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DecodeStatus AMDGPUDisassembler::DecodeSrc32Register(unsigned Val,
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unsigned& RegID) const {
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unsigned &RegID) const {
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// ToDo: deal with out-of range registers
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// ToDo: deal with out-of range registers
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using namespace AMDGPU;
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using namespace AMDGPU;
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if (Val <= 101) {
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if (Val <= 101) {
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return DecodeSgprRegister(Val, RegID);
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return DecodeSgprRegister(Val, RegID, 32);
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} else if ((Val >= 256) && (Val <= 511)) {
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} else if ((Val >= 256) && (Val <= 511)) {
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return DecodeVgprRegister(Val - 256, RegID);
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return DecodeVgprRegister(Val - 256, RegID, 32);
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} else {
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} else {
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switch(Val) {
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switch(Val) {
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case 102: RegID = getMCReg(FLAT_SCR_LO, STI); return MCDisassembler::Success;
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case 102: RegID = getMCReg(FLAT_SCR_LO, STI); return MCDisassembler::Success;
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@ -239,8 +321,40 @@ DecodeStatus AMDGPUDisassembler::DecodeSrcRegister(unsigned Val,
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return MCDisassembler::Fail;
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return MCDisassembler::Fail;
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}
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}
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DecodeStatus AMDGPUDisassembler::DecodeVGPR_32RegisterClass(llvm::MCInst &Inst,
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DecodeStatus AMDGPUDisassembler::DecodeSrc64Register(unsigned Val,
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unsigned Imm,
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unsigned &RegID) const {
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// ToDo: deal with out-of range registers
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using namespace AMDGPU;
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if (Val <= 101) {
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return DecodeSgprRegister(Val, RegID, 64);
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} else if ((Val >= 256) && (Val <= 511)) {
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return DecodeVgprRegister(Val - 256, RegID, 64);
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} else {
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switch(Val) {
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case 102: RegID = getMCReg(FLAT_SCR, STI); return MCDisassembler::Success;
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case 106: RegID = getMCReg(VCC, STI); return MCDisassembler::Success;
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case 126: RegID = getMCReg(EXEC, STI); return MCDisassembler::Success;
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default: return MCDisassembler::Fail;
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}
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}
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return MCDisassembler::Fail;
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}
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DecodeStatus AMDGPUDisassembler::DecodeLiteralConstant(MCInst &Inst,
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uint64_t &Literal) const {
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// For now all literal constants are supposed to be unsigned integer
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// ToDo: deal with signed/unsigned 64-bit integer constants
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// ToDo: deal with float/double constants
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if (Bytes.size() < 8) {
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return MCDisassembler::Fail;
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}
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Literal =
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0 | (Bytes[7] << 24) | (Bytes[6] << 16) | (Bytes[5] << 8) | (Bytes[4] << 0);
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return MCDisassembler::Success;
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}
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DecodeStatus AMDGPUDisassembler::DecodeVGPR_32RegisterClass(llvm::MCInst &Inst,
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unsigned Imm,
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uint64_t Addr) const {
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uint64_t Addr) const {
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unsigned RegID;
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unsigned RegID;
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if (DecodeVgprRegister(Imm, RegID) == MCDisassembler::Success) {
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if (DecodeVgprRegister(Imm, RegID) == MCDisassembler::Success) {
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@ -250,21 +364,30 @@ DecodeStatus AMDGPUDisassembler::DecodeVGPR_32RegisterClass(llvm::MCInst &Inst,
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return MCDisassembler::Fail;
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return MCDisassembler::Fail;
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}
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}
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DecodeStatus AMDGPUDisassembler::DecodeVS_32RegisterClass(MCInst &Inst,
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DecodeStatus AMDGPUDisassembler::DecodeVSRegisterClass(MCInst &Inst,
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unsigned Imm,
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unsigned Imm,
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uint64_t Addr) const {
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uint64_t Addr,
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// ToDo: different opcodes allow different formats og this operands
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bool Is32) const {
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// ToDo: different opcodes allow different formats of this operands
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if ((Imm >= 128) && (Imm <= 208)) {
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if ((Imm >= 128) && (Imm <= 208)) {
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// immediate integer
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// immediate integer
|
||||||
int64_t Val;
|
int64_t Val;
|
||||||
if (DecodeLitInteger(Imm, Val) == MCDisassembler::Success) {
|
if (DecodeImmedInteger(Imm, Val) == MCDisassembler::Success) {
|
||||||
Inst.addOperand(MCOperand::createImm(Val));
|
Inst.addOperand(MCOperand::createImm(Val));
|
||||||
return MCDisassembler::Success;
|
return MCDisassembler::Success;
|
||||||
}
|
}
|
||||||
} else if ((Imm >= 240) && (Imm <= 248)) {
|
} else if ((Imm >= 240) && (Imm <= 248)) {
|
||||||
// immediate float
|
// immediate float/double
|
||||||
uint32_t Val;
|
uint64_t Val;
|
||||||
if (DecodeLitFloat(Imm, Val) == MCDisassembler::Success) {
|
DecodeStatus status;
|
||||||
|
if (Is32) {
|
||||||
|
uint32_t Val32;
|
||||||
|
status = DecodeImmedFloat(Imm, Val32);
|
||||||
|
Val = static_cast<uint64_t>(Val32);
|
||||||
|
} else {
|
||||||
|
status = DecodeImmedDouble(Imm, Val);
|
||||||
|
}
|
||||||
|
if (status == MCDisassembler::Success) {
|
||||||
Inst.addOperand(MCOperand::createImm(Val));
|
Inst.addOperand(MCOperand::createImm(Val));
|
||||||
return MCDisassembler::Success;
|
return MCDisassembler::Success;
|
||||||
}
|
}
|
||||||
|
|
@ -273,17 +396,26 @@ DecodeStatus AMDGPUDisassembler::DecodeVS_32RegisterClass(MCInst &Inst,
|
||||||
// ToDo: implement LDS direct read
|
// ToDo: implement LDS direct read
|
||||||
} else if (Imm == 255) {
|
} else if (Imm == 255) {
|
||||||
// literal constant
|
// literal constant
|
||||||
} else if ((Imm == 125) ||
|
HasLiteral = true;
|
||||||
((Imm >= 209) && (Imm <= 239)) ||
|
uint64_t Literal;
|
||||||
(Imm == 249) ||
|
if (DecodeLiteralConstant(Inst, Literal) == MCDisassembler::Success) {
|
||||||
(Imm == 250) ||
|
Inst.addOperand(MCOperand::createImm(Literal));
|
||||||
|
return MCDisassembler::Success;
|
||||||
|
}
|
||||||
|
return MCDisassembler::Fail;
|
||||||
|
} else if ((Imm == 125) ||
|
||||||
|
((Imm >= 209) && (Imm <= 239)) ||
|
||||||
|
(Imm == 249) ||
|
||||||
|
(Imm == 250) ||
|
||||||
(Imm >= 512)) {
|
(Imm >= 512)) {
|
||||||
// reserved
|
// reserved
|
||||||
return MCDisassembler::Fail;
|
return MCDisassembler::Fail;
|
||||||
} else {
|
} else {
|
||||||
// register
|
// register
|
||||||
unsigned RegID;
|
unsigned RegID;
|
||||||
if (DecodeSrcRegister(Imm, RegID) == MCDisassembler::Success) {
|
DecodeStatus status = Is32 ? DecodeSrc32Register(Imm, RegID)
|
||||||
|
: DecodeSrc64Register(Imm, RegID);
|
||||||
|
if (status == MCDisassembler::Success) {
|
||||||
Inst.addOperand(MCOperand::createReg(RegID));
|
Inst.addOperand(MCOperand::createReg(RegID));
|
||||||
return MCDisassembler::Success;
|
return MCDisassembler::Success;
|
||||||
}
|
}
|
||||||
|
|
@ -291,6 +423,31 @@ DecodeStatus AMDGPUDisassembler::DecodeVS_32RegisterClass(MCInst &Inst,
|
||||||
return MCDisassembler::Fail;
|
return MCDisassembler::Fail;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
DecodeStatus AMDGPUDisassembler::DecodeVS_32RegisterClass(MCInst &Inst,
|
||||||
|
unsigned Imm,
|
||||||
|
uint64_t Addr) const {
|
||||||
|
return DecodeVSRegisterClass(Inst, Imm, Addr, true);
|
||||||
|
}
|
||||||
|
|
||||||
|
DecodeStatus AMDGPUDisassembler::DecodeVS_64RegisterClass(MCInst &Inst,
|
||||||
|
unsigned Imm,
|
||||||
|
uint64_t Addr) const {
|
||||||
|
return DecodeVSRegisterClass(Inst, Imm, Addr, false);
|
||||||
|
}
|
||||||
|
|
||||||
|
DecodeStatus AMDGPUDisassembler::DecodeVReg_64RegisterClass(llvm::MCInst &Inst,
|
||||||
|
unsigned Imm,
|
||||||
|
uint64_t Addr) const {
|
||||||
|
unsigned RegID;
|
||||||
|
if (DecodeVgprRegister(Imm, RegID, 64) == MCDisassembler::Success) {
|
||||||
|
Inst.addOperand(MCOperand::createReg(RegID));
|
||||||
|
return MCDisassembler::Success;
|
||||||
|
}
|
||||||
|
return MCDisassembler::Fail;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
static MCDisassembler *createAMDGPUDisassembler(const Target &T,
|
static MCDisassembler *createAMDGPUDisassembler(const Target &T,
|
||||||
const MCSubtargetInfo &STI,
|
const MCSubtargetInfo &STI,
|
||||||
MCContext &Ctx) {
|
MCContext &Ctx) {
|
||||||
|
|
|
||||||
|
|
@ -25,9 +25,14 @@ namespace llvm {
|
||||||
class MCSubtargetInfo;
|
class MCSubtargetInfo;
|
||||||
|
|
||||||
class AMDGPUDisassembler : public MCDisassembler {
|
class AMDGPUDisassembler : public MCDisassembler {
|
||||||
|
private:
|
||||||
|
/// true if 32-bit literal constant is placed after instruction
|
||||||
|
mutable bool HasLiteral;
|
||||||
|
mutable ArrayRef<uint8_t> Bytes;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
|
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
|
||||||
MCDisassembler(STI, Ctx) {}
|
MCDisassembler(STI, Ctx), HasLiteral(false) {}
|
||||||
|
|
||||||
~AMDGPUDisassembler() {}
|
~AMDGPUDisassembler() {}
|
||||||
|
|
||||||
|
|
@ -35,23 +40,41 @@ namespace llvm {
|
||||||
ArrayRef<uint8_t> Bytes, uint64_t Address,
|
ArrayRef<uint8_t> Bytes, uint64_t Address,
|
||||||
raw_ostream &WS, raw_ostream &CS) const override;
|
raw_ostream &WS, raw_ostream &CS) const override;
|
||||||
|
|
||||||
/// Decode inline float value in VSrc field
|
/// Decode inline float value in SRC field
|
||||||
DecodeStatus DecodeLitFloat(unsigned Imm, uint32_t& F) const;
|
DecodeStatus DecodeImmedFloat(unsigned Imm, uint32_t &F) const;
|
||||||
/// Decode inline integer value in VSrc field
|
/// Decode inline double value in SRC field
|
||||||
DecodeStatus DecodeLitInteger(unsigned Imm, int64_t& I) const;
|
DecodeStatus DecodeImmedDouble(unsigned Imm, uint64_t &D) const;
|
||||||
|
/// Decode inline integer value in SRC field
|
||||||
|
DecodeStatus DecodeImmedInteger(unsigned Imm, int64_t &I) const;
|
||||||
/// Decode VGPR register
|
/// Decode VGPR register
|
||||||
DecodeStatus DecodeVgprRegister(unsigned Val, unsigned& RegID) const;
|
DecodeStatus DecodeVgprRegister(unsigned Val, unsigned &RegID,
|
||||||
|
unsigned Size = 32) const;
|
||||||
/// Decode SGPR register
|
/// Decode SGPR register
|
||||||
DecodeStatus DecodeSgprRegister(unsigned Val, unsigned& RegID) const;
|
DecodeStatus DecodeSgprRegister(unsigned Val, unsigned &RegID,
|
||||||
/// Decode register in VSrc field
|
unsigned Size = 32) const;
|
||||||
DecodeStatus DecodeSrcRegister(unsigned Val, unsigned& RegID) const;
|
/// Decode 32-bit register in SRC field
|
||||||
|
DecodeStatus DecodeSrc32Register(unsigned Val, unsigned &RegID) const;
|
||||||
|
/// Decode 64-bit register in SRC field
|
||||||
|
DecodeStatus DecodeSrc64Register(unsigned Val, unsigned &RegID) const;
|
||||||
|
|
||||||
DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
|
/// Decode literal constant after instruction
|
||||||
|
DecodeStatus DecodeLiteralConstant(MCInst &Inst, uint64_t &Literal) const;
|
||||||
|
|
||||||
|
DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
|
||||||
|
uint64_t Addr) const;
|
||||||
|
|
||||||
|
DecodeStatus DecodeVSRegisterClass(MCInst &Inst, unsigned Imm,
|
||||||
|
uint64_t Addr, bool Is32) const;
|
||||||
|
|
||||||
|
DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
|
||||||
uint64_t Addr) const;
|
uint64_t Addr) const;
|
||||||
|
|
||||||
DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
|
DecodeStatus DecodeVS_64RegisterClass(MCInst &Inst, unsigned Imm,
|
||||||
|
uint64_t Addr) const;
|
||||||
|
|
||||||
|
DecodeStatus DecodeVReg_64RegisterClass(MCInst &Inst, unsigned Imm,
|
||||||
uint64_t Addr) const;
|
uint64_t Addr) const;
|
||||||
};
|
};
|
||||||
} // namespace llvm
|
} // namespace llvm
|
||||||
|
|
||||||
#endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
|
#endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
|
||||||
|
|
|
||||||
|
|
@ -1666,7 +1666,7 @@ class VOP3_C_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName,
|
||||||
}
|
}
|
||||||
|
|
||||||
class VOP3_C_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName,
|
class VOP3_C_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName,
|
||||||
bit HasMods = 0, bit VOP3Only = 0> :
|
bit HasMods = 0, bit VOP3Only = 0> :
|
||||||
VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
|
VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
|
||||||
VOP3ce_vi <op>,
|
VOP3ce_vi <op>,
|
||||||
SIMCInstr <opName#"_e64", SISubtarget.VI> {
|
SIMCInstr <opName#"_e64", SISubtarget.VI> {
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,250 @@
|
||||||
|
# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s
|
||||||
|
|
||||||
|
# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
|
||||||
|
0x00 0x00 0x00 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
|
||||||
|
0x00 0x6a 0x00 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_mov_b32_e32 v2, v1 ; encoding: [0x01,0x03,0x04,0x7e]
|
||||||
|
0x01 0x03 0x04 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_mov_b32_e32 v1, 0.5 ; encoding: [0xf0,0x02,0x02,0x7e]
|
||||||
|
0xf0 0x02 0x02 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_mov_b32_e32 v15, s100 ; encoding: [0x64,0x02,0x1e,0x7e]
|
||||||
|
0x64 0x02 0x1e 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_mov_b32_e32 v90, flat_scratch_lo ; encoding: [0x66,0x02,0xb4,0x7e]
|
||||||
|
0x66 0x02 0xb4 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_mov_b32_e32 v150, vcc_lo ; encoding: [0x6a,0x02,0x2c,0x7f]
|
||||||
|
0x6a 0x02 0x2c 0x7f
|
||||||
|
|
||||||
|
# CHECK: v_mov_b32_e32 v199, exec_lo ; encoding: [0x7e,0x02,0x8e,0x7f]
|
||||||
|
0x7e 0x02 0x8e 0x7f
|
||||||
|
|
||||||
|
# CHECK: v_mov_b32_e32 v222, m0 ; encoding: [0x7c,0x02,0xbc,0x7f]
|
||||||
|
0x7c 0x02 0xbc 0x7f
|
||||||
|
|
||||||
|
# CHECK: v_mov_b32_e32 v255, -13 ; encoding: [0xcd,0x02,0xfe,0x7f]
|
||||||
|
0xcd 0x02 0xfe 0x7f
|
||||||
|
|
||||||
|
# CHECK: v_cvt_f32_i32_e32 v153, s98 ; encoding: [0x62,0x0a,0x32,0x7f]
|
||||||
|
0x62 0x0a 0x32 0x7f
|
||||||
|
|
||||||
|
# CHECK: v_cvt_f32_u32_e32 v33, -4.0 ; encoding: [0xf7,0x0c,0x42,0x7e]
|
||||||
|
0xf7 0x0c 0x42 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_cvt_i32_f64_e32 v2, s[0:1] ; encoding: [0x00,0x06,0x04,0x7e]
|
||||||
|
0x00 0x06 0x04 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_cvt_u32_f32_e32 v123, vcc_hi ; encoding: [0x6b,0x0e,0xf6,0x7e]
|
||||||
|
0x6b 0x0e 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_cvt_i32_f32_e32 v123, flat_scratch_lo ; encoding: [0x66,0x10,0xf6,0x7e]
|
||||||
|
0x66 0x10 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_cvt_rpi_i32_f32_e32 v123, s101 ; encoding: [0x65,0x18,0xf6,0x7e]
|
||||||
|
0x65 0x18 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_cvt_flr_i32_f32_e32 v123, -4.0 ; encoding: [0xf7,0x1a,0xf6,0x7e]
|
||||||
|
0xf7 0x1a 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_cvt_f32_f64_e32 v123, vcc ; encoding: [0x6a,0x1e,0xf6,0x7e]
|
||||||
|
0x6a 0x1e 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_cvt_u32_f64_e32 v123, exec ; encoding: [0x7e,0x2a,0xf6,0x7e]
|
||||||
|
0x7e 0x2a 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_fract_f32_e32 v123, m0 ; encoding: [0x7c,0x36,0xf6,0x7e]
|
||||||
|
0x7c 0x36 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_trunc_f32_e32 v123, exec_lo ; encoding: [0x7e,0x38,0xf6,0x7e]
|
||||||
|
0x7e 0x38 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_ceil_f32_e32 v123, exec_hi ; encoding: [0x7f,0x3a,0xf6,0x7e]
|
||||||
|
0x7f 0x3a 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_rndne_f32_e32 v123, 0 ; encoding: [0x80,0x3c,0xf6,0x7e]
|
||||||
|
0x80 0x3c 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_floor_f32_e32 v123, -0.5 ; encoding: [0xf1,0x3e,0xf6,0x7e]
|
||||||
|
0xf1 0x3e 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_exp_f32_e32 v123, 1.0 ; encoding: [0xf2,0x40,0xf6,0x7e]
|
||||||
|
0xf2 0x40 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_log_f32_e32 v123, -1.0 ; encoding: [0xf3,0x42,0xf6,0x7e]
|
||||||
|
0xf3 0x42 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_rcp_f32_e32 v123, 2.0 ; encoding: [0xf4,0x44,0xf6,0x7e]
|
||||||
|
0xf4 0x44 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_rcp_iflag_f32_e32 v123, -2.0 ; encoding: [0xf5,0x46,0xf6,0x7e]
|
||||||
|
0xf5 0x46 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_rsq_f32_e32 v123, 4.0 ; encoding: [0xf6,0x48,0xf6,0x7e]
|
||||||
|
0xf6 0x48 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_sqrt_f32_e32 v123, v12 ; encoding: [0x0c,0x4f,0xf6,0x7e]
|
||||||
|
0x0c 0x4f 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_sin_f32_e32 v123, v12 ; encoding: [0x0c,0x53,0xf6,0x7e]
|
||||||
|
0x0c 0x53 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_cos_f32_e32 v123, v12 ; encoding: [0x0c,0x55,0xf6,0x7e]
|
||||||
|
0x0c 0x55 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_not_b32_e32 v123, v12 ; encoding: [0x0c,0x57,0xf6,0x7e]
|
||||||
|
0x0c 0x57 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_bfrev_b32_e32 v123, v12 ; encoding: [0x0c,0x59,0xf6,0x7e]
|
||||||
|
0x0c 0x59 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_ffbh_u32_e32 v123, v12 ; encoding: [0x0c,0x5b,0xf6,0x7e]
|
||||||
|
0x0c 0x5b 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_ffbl_b32_e32 v123, v12 ; encoding: [0x0c,0x5d,0xf6,0x7e]
|
||||||
|
0x0c 0x5d 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_ffbh_i32_e32 v123, v12 ; encoding: [0x0c,0x5f,0xf6,0x7e]
|
||||||
|
0x0c 0x5f 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_frexp_exp_i32_f64_e32 v123, 2.0 ; encoding: [0xf4,0x60,0xf6,0x7e]
|
||||||
|
0xf4 0x60 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_frexp_exp_i32_f32_e32 v123, s33 ; encoding: [0x21,0x66,0xf6,0x7e]
|
||||||
|
0x21 0x66 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_frexp_mant_f32_e32 v123, s33 ; encoding: [0x21,0x68,0xf6,0x7e]
|
||||||
|
0x21 0x68 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_movreld_b32_e32 v123, s33 ; encoding: [0x21,0x6c,0xf6,0x7e]
|
||||||
|
0x21 0x6c 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_movrels_b32_e32 v123, s33 ; encoding: [0x21,0x6e,0xf6,0x7e]
|
||||||
|
0x21 0x6e 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_movrelsd_b32_e32 v123, s33 ; encoding: [0x21,0x70,0xf6,0x7e]
|
||||||
|
0x21 0x70 0xf6 0x7e
|
||||||
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|
||||||
|
# CHECK: v_cvt_f16_f32_e32 v123, flat_scratch_hi ; encoding: [0x67,0x14,0xf6,0x7e]
|
||||||
|
0x67 0x14 0xf6 0x7e
|
||||||
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||||||
|
# CHECK: v_cvt_f32_f16_e32 v123, s55 ; encoding: [0x37,0x16,0xf6,0x7e]
|
||||||
|
0x37 0x16 0xf6 0x7e
|
||||||
|
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||||||
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# CHECK: v_cvt_off_f32_i4_e32 v123, v12 ; encoding: [0x0c,0x1d,0xf6,0x7e]
|
||||||
|
0x0c 0x1d 0xf6 0x7e
|
||||||
|
|
||||||
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# CHECK: v_cvt_f32_ubyte0_e32 v123, v12 ; encoding: [0x0c,0x23,0xf6,0x7e]
|
||||||
|
0x0c 0x23 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_cvt_f32_ubyte1_e32 v123, v12 ; encoding: [0x0c,0x25,0xf6,0x7e]
|
||||||
|
0x0c 0x25 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_cvt_f32_ubyte2_e32 v123, v12 ; encoding: [0x0c,0x27,0xf6,0x7e]
|
||||||
|
0x0c 0x27 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_cvt_f32_ubyte3_e32 v123, v12 ; encoding: [0x0c,0x29,0xf6,0x7e]
|
||||||
|
0x0c 0x29 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_cvt_f64_i32_e32 v[222:223], 1.0 ; encoding: [0xf2,0x08,0xbc,0x7f]
|
||||||
|
0xf2 0x08 0xbc 0x7f
|
||||||
|
|
||||||
|
# CHECK: v_cvt_f64_i32_e32 v[222:223], exec_hi ; encoding: [0x7f,0x08,0xbc,0x7f]
|
||||||
|
0x7f 0x08 0xbc 0x7f
|
||||||
|
|
||||||
|
# CHECK: v_cvt_f64_f32_e32 v[222:223], s33 ; encoding: [0x21,0x20,0xbc,0x7f]
|
||||||
|
0x21 0x20 0xbc 0x7f
|
||||||
|
|
||||||
|
# CHECK: v_cvt_f64_u32_e32 v[222:223], s33 ; encoding: [0x21,0x2c,0xbc,0x7f]
|
||||||
|
0x21 0x2c 0xbc 0x7f
|
||||||
|
|
||||||
|
# CHECK: v_rcp_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x4a,0xbc,0x7f]
|
||||||
|
0x16 0x4a 0xbc 0x7f
|
||||||
|
|
||||||
|
# CHECK: v_rsq_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x4c,0xbc,0x7f]
|
||||||
|
0x16 0x4c 0xbc 0x7f
|
||||||
|
|
||||||
|
# CHECK: v_sqrt_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x50,0xbc,0x7f]
|
||||||
|
0x16 0x50 0xbc 0x7f
|
||||||
|
|
||||||
|
# CHECK: v_frexp_mant_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x62,0xbc,0x7f]
|
||||||
|
0x16 0x62 0xbc 0x7f
|
||||||
|
|
||||||
|
# CHECK: v_fract_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x64,0xbc,0x7f]
|
||||||
|
0x16 0x64 0xbc 0x7f
|
||||||
|
|
||||||
|
# CHECK: v_cvt_f16_u16_e32 v123, 23 ; encoding: [0x97,0x72,0xf6,0x7e]
|
||||||
|
0x97 0x72 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_cvt_f16_i16_e32 v123, vcc_hi ; encoding: [0x6b,0x74,0xf6,0x7e]
|
||||||
|
0x6b 0x74 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_cvt_u16_f16_e32 v123, m0 ; encoding: [0x7c,0x76,0xf6,0x7e]
|
||||||
|
0x7c 0x76 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_cvt_i16_f16_e32 v123, exec_lo ; encoding: [0x7e,0x78,0xf6,0x7e]
|
||||||
|
0x7e 0x78 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_rcp_f16_e32 v123, 1.0 ; encoding: [0xf2,0x7a,0xf6,0x7e]
|
||||||
|
0xf2 0x7a 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_sqrt_f16_e32 v123, 4.0 ; encoding: [0xf6,0x7c,0xf6,0x7e]
|
||||||
|
0xf6 0x7c 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_rsq_f16_e32 v123, -1.0 ; encoding: [0xf3,0x7e,0xf6,0x7e]
|
||||||
|
0xf3 0x7e 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_log_f16_e32 v123, s33 ; encoding: [0x21,0x80,0xf6,0x7e]
|
||||||
|
0x21 0x80 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_exp_f16_e32 v123, v12 ; encoding: [0x0c,0x83,0xf6,0x7e]
|
||||||
|
0x0c 0x83 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_frexp_mant_f16_e32 v123, v12 ; encoding: [0x0c,0x85,0xf6,0x7e]
|
||||||
|
0x0c 0x85 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_frexp_exp_i16_f16_e32 v123, v12 ; encoding: [0x0c,0x87,0xf6,0x7e]
|
||||||
|
0x0c 0x87 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_floor_f16_e32 v123, v12 ; encoding: [0x0c,0x89,0xf6,0x7e]
|
||||||
|
0x0c 0x89 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_ceil_f16_e32 v123, v12 ; encoding: [0x0c,0x8b,0xf6,0x7e]
|
||||||
|
0x0c 0x8b 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_trunc_f16_e32 v123, s33 ; encoding: [0x21,0x8c,0xf6,0x7e]
|
||||||
|
0x21 0x8c 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_rndne_f16_e32 v123, s33 ; encoding: [0x21,0x8e,0xf6,0x7e]
|
||||||
|
0x21 0x8e 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_fract_f16_e32 v123, s33 ; encoding: [0x21,0x90,0xf6,0x7e]
|
||||||
|
0x21 0x90 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_sin_f16_e32 v123, s33 ; encoding: [0x21,0x92,0xf6,0x7e]
|
||||||
|
0x21 0x92 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_cos_f16_e32 v123, s33 ; encoding: [0x21,0x94,0xf6,0x7e]
|
||||||
|
0x21 0x94 0xf6 0x7e
|
||||||
|
|
||||||
|
# CHECK: v_mov_b32_e32 v2, 0x75bcd15 ; encoding: [0xff,0x02,0x04,0x7e,0x15,0xcd,0x5b,0x07]
|
||||||
|
0xff 0x02 0x04 0x7e 0x15 0xcd 0x5b 0x07
|
||||||
|
|
||||||
|
# CHECK: v_cvt_f32_u32_e32 v33, 0x4236b732 ; encoding: [0xff,0x0c,0x42,0x7e,0x32,0xb7,0x36,0x42]
|
||||||
|
0xff 0x0c 0x42 0x7e 0x32 0xb7 0x36 0x42
|
||||||
|
|
||||||
|
# CHECK: v_cvt_i32_f64_e32 v2, 0x4236b732 ; encoding: [0xff,0x06,0x04,0x7e,0x32,0xb7,0x36,0x42]
|
||||||
|
0xff 0x06 0x04 0x7e 0x32 0xb7 0x36 0x42
|
||||||
|
|
||||||
|
# CHECK: v_cvt_f16_u16_e32 v123, 0x3ade68b1 ; encoding: [0xff,0x72,0xf6,0x7e,0xb1,0x68,0xde,0x3a]
|
||||||
|
0xff 0x72 0xf6 0x7e 0xb1 0x68 0xde 0x3a
|
||||||
|
|
||||||
|
# CHECK: v_cvt_f16_i16_e32 v123, 0x21c2 ; encoding: [0xff,0x74,0xf6,0x7e,0xc2,0x21,0x00,0x00]
|
||||||
|
0xff 0x74 0xf6 0x7e 0xc2 0x21 0x00 0x00
|
||||||
|
|
||||||
|
# CHECK: v_cvt_u16_f16_e32 v123, 0x3f200000 ; encoding: [0xff,0x76,0xf6,0x7e,0x00,0x00,0x20,0x3f]
|
||||||
|
0xff 0x76 0xf6 0x7e 0x00 0x00 0x20 0x3f
|
||||||
Loading…
Reference in New Issue