Mark flag neverHasSideEffects of pattern-less instructions that do not have
any side effects. llvm-svn: 153551
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8b4140d712
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@ -365,6 +365,7 @@ class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
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FI<op, (outs RC:$rt), (ins Imm:$imm16),
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FI<op, (outs RC:$rt), (ins Imm:$imm16),
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!strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
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!strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
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let rs = 0;
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let rs = 0;
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let neverHasSideEffects = 1;
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}
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}
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class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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@ -555,6 +556,7 @@ class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
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let shamt = 0;
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let shamt = 0;
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let isCommutable = 1;
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let isCommutable = 1;
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let Defs = DefRegs;
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let Defs = DefRegs;
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let neverHasSideEffects = 1;
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}
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}
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class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
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class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
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@ -582,6 +584,7 @@ class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
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let rt = 0;
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let rt = 0;
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let shamt = 0;
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let shamt = 0;
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let Uses = UseRegs;
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let Uses = UseRegs;
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let neverHasSideEffects = 1;
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}
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}
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class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
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class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
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@ -592,6 +595,7 @@ class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
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let rd = 0;
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let rd = 0;
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let shamt = 0;
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let shamt = 0;
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let Defs = DefRegs;
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let Defs = DefRegs;
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let neverHasSideEffects = 1;
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}
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}
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class EffectiveAddress<string instr_asm, RegisterClass RC, Operand Mem> :
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class EffectiveAddress<string instr_asm, RegisterClass RC, Operand Mem> :
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@ -635,6 +639,7 @@ class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
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let rs = 0;
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let rs = 0;
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let shamt = sa;
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let shamt = sa;
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let Predicates = [HasSwap];
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let Predicates = [HasSwap];
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let neverHasSideEffects = 1;
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}
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}
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// Read Hardware
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// Read Hardware
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