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Support/ELF: Add R_AMDGPU_GOTPCREL relocation 

Summary:
We will start generating this in a future patch.

Reviewers: arsenm, kzhuravl, rafael, ruiu, tony-tye

Subscribers: arsenm, llvm-commits, kzhuravl

Differential Revision: http://reviews.llvm.org/D21482

llvm-svn: 273628
This commit is contained in:
Tom Stellard 2016-06-23 23:11:29 +00:00
parent 606f178aeb
commit 14416ae6cd
4 changed files with 16 additions and 0 deletions
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4
llvm/docs/CodeGenerator.rst
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@ -2676,6 +2676,9 @@ Following notations are used for specifying relocation calculations:
* **A** --- Represents the addend used to compute the value of the relocatable * **A** --- Represents the addend used to compute the value of the relocatable
field field
* **G** --- Represents the offset into the global offset table at which the
relocation entry’s symbol will reside during execution.
* **GOT** --- Represents the address of the global offset table.
* **P** --- Represents the place (section offset or address) of the storage unit * **P** --- Represents the place (section offset or address) of the storage unit
being relocated (computed using ``r_offset``) being relocated (computed using ``r_offset``)
* **S** --- Represents the value of the symbol whose index resides in the * **S** --- Represents the value of the symbol whose index resides in the
@ -2694,4 +2697,5 @@ supported relocation types:
``R_AMDGPU_REL32`` 4 ``word32`` S + A - P ``R_AMDGPU_REL32`` 4 ``word32`` S + A - P
``R_AMDGPU_REL64`` 5 ``word64`` S + A - P ``R_AMDGPU_REL64`` 5 ``word64`` S + A - P
``R_AMDGPU_ABS32`` 6 ``word32`` S + A ``R_AMDGPU_ABS32`` 6 ``word32`` S + A
``R_AMDGPU_GOTPCREL`` 7 ``word32`` G + GOT + A - P
===================== ===== ========== ==================== ===================== ===== ========== ====================

1
llvm/include/llvm/Support/ELFRelocs/AMDGPU.def
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@ -9,3 +9,4 @@ ELF_RELOC(R_AMDGPU_ABS64, 3)
ELF_RELOC(R_AMDGPU_REL32, 4) ELF_RELOC(R_AMDGPU_REL32, 4)
ELF_RELOC(R_AMDGPU_REL64, 5) ELF_RELOC(R_AMDGPU_REL64, 5)
ELF_RELOC(R_AMDGPU_ABS32, 6) ELF_RELOC(R_AMDGPU_ABS32, 6)
ELF_RELOC(R_AMDGPU_GOTPCREL, 7)

7
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
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@ -45,6 +45,13 @@ unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD1") if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD1")
return ELF::R_AMDGPU_ABS32_HI; return ELF::R_AMDGPU_ABS32_HI;
switch (Target.getAccessVariant()) {
default:
break;
case MCSymbolRefExpr::VK_GOTPCREL:
return ELF::R_AMDGPU_GOTPCREL;
}
switch (Fixup.getKind()) { switch (Fixup.getKind()) {
default: break; default: break;
case FK_PCRel_4: case FK_PCRel_4:

4
llvm/test/MC/AMDGPU/reloc.s
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@ -3,10 +3,14 @@
// CHECK: Relocations [ // CHECK: Relocations [
// CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0 // CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0
// CHECK: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0 // CHECK: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0
// CHECK: R_AMDGPU_GOTPCREL global_var 0x0
// CHECK: ] // CHECK: ]
kernel: kernel:
s_mov_b32 s0, SCRATCH_RSRC_DWORD0 s_mov_b32 s0, SCRATCH_RSRC_DWORD0
s_mov_b32 s1, SCRATCH_RSRC_DWORD1 s_mov_b32 s1, SCRATCH_RSRC_DWORD1
s_mov_b32 s2, global_var@GOTPCREL
.globl global_var
.globl SCRATCH_RSRC_DWORD0 .globl SCRATCH_RSRC_DWORD0