Support/ELF: Add R_AMDGPU_GOTPCREL relocation
Summary: We will start generating this in a future patch. Reviewers: arsenm, kzhuravl, rafael, ruiu, tony-tye Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21482 llvm-svn: 273628
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@ -2676,6 +2676,9 @@ Following notations are used for specifying relocation calculations:
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* **A** --- Represents the addend used to compute the value of the relocatable
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* **A** --- Represents the addend used to compute the value of the relocatable
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field
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field
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* **G** --- Represents the offset into the global offset table at which the
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relocation entry’s symbol will reside during execution.
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* **GOT** --- Represents the address of the global offset table.
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* **P** --- Represents the place (section offset or address) of the storage unit
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* **P** --- Represents the place (section offset or address) of the storage unit
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being relocated (computed using ``r_offset``)
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being relocated (computed using ``r_offset``)
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* **S** --- Represents the value of the symbol whose index resides in the
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* **S** --- Represents the value of the symbol whose index resides in the
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@ -2694,4 +2697,5 @@ supported relocation types:
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``R_AMDGPU_REL32`` 4 ``word32`` S + A - P
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``R_AMDGPU_REL32`` 4 ``word32`` S + A - P
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``R_AMDGPU_REL64`` 5 ``word64`` S + A - P
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``R_AMDGPU_REL64`` 5 ``word64`` S + A - P
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``R_AMDGPU_ABS32`` 6 ``word32`` S + A
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``R_AMDGPU_ABS32`` 6 ``word32`` S + A
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``R_AMDGPU_GOTPCREL`` 7 ``word32`` G + GOT + A - P
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===================== ===== ========== ====================
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===================== ===== ========== ====================
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@ -9,3 +9,4 @@ ELF_RELOC(R_AMDGPU_ABS64, 3)
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ELF_RELOC(R_AMDGPU_REL32, 4)
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ELF_RELOC(R_AMDGPU_REL32, 4)
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ELF_RELOC(R_AMDGPU_REL64, 5)
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ELF_RELOC(R_AMDGPU_REL64, 5)
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ELF_RELOC(R_AMDGPU_ABS32, 6)
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ELF_RELOC(R_AMDGPU_ABS32, 6)
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ELF_RELOC(R_AMDGPU_GOTPCREL, 7)
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@ -45,6 +45,13 @@ unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
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if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD1")
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if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD1")
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return ELF::R_AMDGPU_ABS32_HI;
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return ELF::R_AMDGPU_ABS32_HI;
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switch (Target.getAccessVariant()) {
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default:
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break;
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case MCSymbolRefExpr::VK_GOTPCREL:
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return ELF::R_AMDGPU_GOTPCREL;
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}
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switch (Fixup.getKind()) {
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switch (Fixup.getKind()) {
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default: break;
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default: break;
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case FK_PCRel_4:
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case FK_PCRel_4:
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@ -3,10 +3,14 @@
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// CHECK: Relocations [
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// CHECK: Relocations [
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// CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0
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// CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0
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// CHECK: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0
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// CHECK: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0
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// CHECK: R_AMDGPU_GOTPCREL global_var 0x0
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// CHECK: ]
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// CHECK: ]
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kernel:
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kernel:
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s_mov_b32 s0, SCRATCH_RSRC_DWORD0
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s_mov_b32 s0, SCRATCH_RSRC_DWORD0
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s_mov_b32 s1, SCRATCH_RSRC_DWORD1
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s_mov_b32 s1, SCRATCH_RSRC_DWORD1
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s_mov_b32 s2, global_var@GOTPCREL
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.globl global_var
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.globl SCRATCH_RSRC_DWORD0
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.globl SCRATCH_RSRC_DWORD0
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