Codegen: Fix llvm.*absdiff semantic.
Fixes the overflow case of llvm.*absdiff intrinsic also updats the tests and LangRef.rst accordingly. Differential Revision: http://reviews.llvm.org/D11678 llvm-svn: 248483
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Mohammad Shahid
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2720593ab4
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@ -10920,16 +10920,19 @@ This is an overloaded intrinsic. The loaded data is a vector of any integer bit
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Overview:
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"""""""""
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The ``llvm.uabsdiff`` intrinsic returns a vector result of the absolute difference of
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the two operands, treating them both as unsigned integers.
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The ``llvm.uabsdiff`` intrinsic returns a vector result of the absolute difference
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of the two operands, treating them both as unsigned integers. The intermediate
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calculations are computed using infinitely precise unsigned arithmetic. The final
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result will be truncated to the given type.
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The ``llvm.sabsdiff`` intrinsic returns a vector result of the absolute difference of
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the two operands, treating them both as signed integers.
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the two operands, treating them both as signed integers. If the result overflows, the
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behavior is undefined.
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.. note::
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These intrinsics are primarily used during the code generation stage of compilation.
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They are generated by compiler passes such as the Loop and SLP vectorizers.it is not
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They are generated by compiler passes such as the Loop and SLP vectorizers. It is not
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recommended for users to create them manually.
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Arguments:
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@ -10946,19 +10949,19 @@ The expression::
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is equivalent to::
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%sub = sub <4 x i32> %a, %b
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%ispos = icmp ugt <4 x i32> %sub, <i32 -1, i32 -1, i32 -1, i32 -1>
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%neg = sub <4 x i32> zeroinitializer, %sub
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%1 = select <4 x i1> %ispos, <4 x i32> %sub, <4 x i32> %neg
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%1 = zext <4 x i32> %a to <4 x i64>
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%2 = zext <4 x i32> %b to <4 x i64>
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%sub = sub <4 x i64> %1, %2
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%trunc = trunc <4 x i64> to <4 x i32>
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Similarly the expression::
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and the expression::
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call <4 x i32> @llvm.sabsdiff.v4i32(<4 x i32> %a, <4 x i32> %b)
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is equivalent to::
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%sub = sub nsw <4 x i32> %a, %b
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%ispos = icmp sgt <4 x i32> %sub, <i32 -1, i32 -1, i32 -1, i32 -1>
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%ispos = icmp sge <4 x i32> %sub, zeroinitializer
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%neg = sub nsw <4 x i32> zeroinitializer, %sub
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%1 = select <4 x i1> %ispos, <4 x i32> %sub, <4 x i32> %neg
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@ -723,24 +723,30 @@ SDValue VectorLegalizer::Expand(SDValue Op) {
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SDValue VectorLegalizer::ExpandABSDIFF(SDValue Op) {
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SDLoc dl(Op);
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SDValue Tmp1, Tmp2, Tmp3, Tmp4;
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SDValue Op0 = Op.getOperand(0);
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SDValue Op1 = Op.getOperand(1);
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EVT VT = Op.getValueType();
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SDNodeFlags Flags;
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Flags.setNoSignedWrap(Op->getOpcode() == ISD::SABSDIFF);
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Tmp2 = Op.getOperand(0);
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Tmp3 = Op.getOperand(1);
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Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp3, &Flags);
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Tmp2 =
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DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), Tmp1, &Flags);
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Tmp4 = DAG.getNode(
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ISD::SETCC, dl,
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TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), Tmp2,
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DAG.getConstant(0, dl, VT),
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DAG.getCondCode(Op->getOpcode() == ISD::SABSDIFF ? ISD::SETLT
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: ISD::SETULT));
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Tmp1 = DAG.getNode(ISD::VSELECT, dl, VT, Tmp4, Tmp1, Tmp2);
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return Tmp1;
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// For unsigned intrinsic, promote the type to handle unsigned overflow.
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bool isUabsdiff = (Op->getOpcode() == ISD::UABSDIFF);
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if (isUabsdiff) {
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VT = VT.widenIntegerVectorElementType(*DAG.getContext());
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Op0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op0);
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Op1 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op1);
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}
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SDNodeFlags Flags;
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Flags.setNoSignedWrap(!isUabsdiff);
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SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op0, Op1, &Flags);
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if (isUabsdiff)
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return DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Sub);
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SDValue Cmp =
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DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(DAG.getDataLayout(),
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*DAG.getContext(), VT),
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Sub, DAG.getConstant(0, dl, VT), DAG.getCondCode(ISD::SETGE));
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SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), Sub, &Flags);
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return DAG.getNode(ISD::VSELECT, dl, VT, Cmp, Sub, Neg);
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}
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SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
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@ -0,0 +1,181 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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declare <4 x i8> @llvm.uabsdiff.v4i8(<4 x i8>, <4 x i8>)
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define <4 x i8> @test_uabsdiff_v4i8_expand(<4 x i8> %a1, <4 x i8> %a2) {
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; CHECK-LABEL: test_uabsdiff_v4i8_expand
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; CHECK: pshufd
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; CHECK: movd
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; CHECK: subl
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; CHECK: punpckldq
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; CHECK-DAG: movd %xmm1, [[SRC:%.*]]
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; CHECK-DAG: movd %xmm0, [[DST:%.*]]
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; CHECK: subl [[SRC]], [[DST]]
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; CHECK: movd
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; CHECK: pshufd
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; CHECK: movd
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; CHECK: punpckldq
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; CHECK: movdqa
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; CHECK: retq
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%1 = call <4 x i8> @llvm.uabsdiff.v4i8(<4 x i8> %a1, <4 x i8> %a2)
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ret <4 x i8> %1
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}
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declare <4 x i8> @llvm.sabsdiff.v4i8(<4 x i8>, <4 x i8>)
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define <4 x i8> @test_sabsdiff_v4i8_expand(<4 x i8> %a1, <4 x i8> %a2) {
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; CHECK-LABEL: test_sabsdiff_v4i8_expand
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; CHECK: psubd
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; CHECK: pcmpgtd
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; CHECK: pcmpeqd
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; CHECK: pxor
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; CHECK-DAG: psubd {{%xmm[0-9]+}}, [[SRC1:%xmm[0-9]+]]
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; CHECK-DAG: pandn {{%xmm[0-9]+}}, [[SRC2:%xmm[0-9]+]]
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; CHECK-DAG: pandn [[SRC1]], [[DST:%xmm[0-9]+]]
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; CHECK: por [[SRC2]], [[DST]]
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; CHECK: retq
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%1 = call <4 x i8> @llvm.sabsdiff.v4i8(<4 x i8> %a1, <4 x i8> %a2)
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ret <4 x i8> %1
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}
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declare <8 x i8> @llvm.sabsdiff.v8i8(<8 x i8>, <8 x i8>)
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define <8 x i8> @test_sabsdiff_v8i8_expand(<8 x i8> %a1, <8 x i8> %a2) {
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; CHECK-LABEL: test_sabsdiff_v8i8_expand
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; CHECK: psubw
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; CHECK: pcmpgtw
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; CHECK: pcmpeqd
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; CHECK: pxor
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; CHECK-DAG: psubw {{%xmm[0-9]+}}, [[SRC1:%xmm[0-9]+]]
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; CHECK-DAG: pandn {{%xmm[0-9]+}}, [[SRC2:%xmm[0-9]+]]
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; CHECK-DAG: pandn [[SRC1]], [[DST:%xmm[0-9]+]]
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; CHECK: por [[SRC2]], [[DST]]
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; CHECK: retq
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%1 = call <8 x i8> @llvm.sabsdiff.v8i8(<8 x i8> %a1, <8 x i8> %a2)
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ret <8 x i8> %1
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}
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declare <16 x i8> @llvm.uabsdiff.v16i8(<16 x i8>, <16 x i8>)
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define <16 x i8> @test_uabsdiff_v16i8_expand(<16 x i8> %a1, <16 x i8> %a2) {
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; CHECK-LABEL: test_uabsdiff_v16i8_expand
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; CHECK: movd
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; CHECK: movzbl
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; CHECK: movzbl
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; CHECK: subl
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; CHECK: punpcklbw
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; CHECK: retq
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%1 = call <16 x i8> @llvm.uabsdiff.v16i8(<16 x i8> %a1, <16 x i8> %a2)
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ret <16 x i8> %1
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}
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declare <8 x i16> @llvm.uabsdiff.v8i16(<8 x i16>, <8 x i16>)
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define <8 x i16> @test_uabsdiff_v8i16_expand(<8 x i16> %a1, <8 x i16> %a2) {
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; CHECK-LABEL: test_uabsdiff_v8i16_expand
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; CHECK: pextrw
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; CHECK: pextrw
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; CHECK: subl
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; CHECK: punpcklwd
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; CHECK: retq
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%1 = call <8 x i16> @llvm.uabsdiff.v8i16(<8 x i16> %a1, <8 x i16> %a2)
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ret <8 x i16> %1
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}
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declare <8 x i16> @llvm.sabsdiff.v8i16(<8 x i16>, <8 x i16>)
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define <8 x i16> @test_sabsdiff_v8i16_expand(<8 x i16> %a1, <8 x i16> %a2) {
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; CHECK-LABEL: test_sabsdiff_v8i16_expand
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; CHECK: psubw
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; CHECK: pcmpgtw
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; CHECK: pcmpeqd
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; CHECK: pxor
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; CHECK-DAG: psubw {{%xmm[0-9]+}}, [[SRC1:%xmm[0-9]+]]
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; CHECK-DAG: pandn {{%xmm[0-9]+}}, [[SRC2:%xmm[0-9]+]]
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; CHECK-DAG: pandn [[SRC1]], [[DST:%xmm[0-9]+]]
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; CHECK: por [[SRC2]], [[DST]]
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; CHECK: retq
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%1 = call <8 x i16> @llvm.sabsdiff.v8i16(<8 x i16> %a1, <8 x i16> %a2)
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ret <8 x i16> %1
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}
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declare <4 x i32> @llvm.sabsdiff.v4i32(<4 x i32>, <4 x i32>)
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define <4 x i32> @test_sabsdiff_v4i32_expand(<4 x i32> %a1, <4 x i32> %a2) {
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; CHECK-LABEL: test_sabsdiff_v4i32_expand
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; CHECK: psubd
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; CHECK: pcmpgtd
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; CHECK: pcmpeqd
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; CHECK: pxor
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; CHECK-DAG: psubd {{%xmm[0-9]+}}, [[SRC1:%xmm[0-9]+]]
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; CHECK-DAG: pandn {{%xmm[0-9]+}}, [[SRC2:%xmm[0-9]+]]
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; CHECK-DAG: pandn [[SRC1]], [[DST:%xmm[0-9]+]]
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; CHECK: por [[SRC2]], [[DST]]
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; CHECK: retq
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%1 = call <4 x i32> @llvm.sabsdiff.v4i32(<4 x i32> %a1, <4 x i32> %a2)
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ret <4 x i32> %1
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}
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declare <4 x i32> @llvm.uabsdiff.v4i32(<4 x i32>, <4 x i32>)
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define <4 x i32> @test_uabsdiff_v4i32_expand(<4 x i32> %a1, <4 x i32> %a2) {
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; CHECK-LABEL: test_uabsdiff_v4i32_expand
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; CHECK: pshufd
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; CHECK: movd
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; CHECK: subl
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; CHECK: punpckldq
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; CHECK-DAG: movd %xmm1, [[SRC:%.*]]
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; CHECK-DAG: movd %xmm0, [[DST:%.*]]
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; CHECK: subl [[SRC]], [[DST]]
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; CHECK: movd
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; CHECK: pshufd
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; CHECK: movd
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; CHECK: punpckldq
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; CHECK: movdqa
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; CHECK: retq
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%1 = call <4 x i32> @llvm.uabsdiff.v4i32(<4 x i32> %a1, <4 x i32> %a2)
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ret <4 x i32> %1
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}
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declare <2 x i32> @llvm.sabsdiff.v2i32(<2 x i32>, <2 x i32>)
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define <2 x i32> @test_sabsdiff_v2i32_expand(<2 x i32> %a1, <2 x i32> %a2) {
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; CHECK-LABEL: test_sabsdiff_v2i32_expand
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; CHECK: psubq
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; CHECK: pcmpgtd
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; CHECK: pcmpeqd
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; CHECK: pxor
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; CHECK-DAG: psubq {{%xmm[0-9]+}}, [[SRC1:%xmm[0-9]+]]
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; CHECK-DAG: pandn {{%xmm[0-9]+}}, [[SRC2:%xmm[0-9]+]]
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; CHECK-DAG: pandn [[SRC1]], [[DST:%xmm[0-9]+]]
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; CHECK: por [[SRC2]], [[DST]]
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; CHECK: retq
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%1 = call <2 x i32> @llvm.sabsdiff.v2i32(<2 x i32> %a1, <2 x i32> %a2)
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ret <2 x i32> %1
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}
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declare <2 x i64> @llvm.sabsdiff.v2i64(<2 x i64>, <2 x i64>)
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define <2 x i64> @test_sabsdiff_v2i64_expand(<2 x i64> %a1, <2 x i64> %a2) {
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; CHECK-LABEL: test_sabsdiff_v2i64_expand
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; CHECK: psubq
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; CHECK: pcmpgtd
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; CHECK: pcmpeqd
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; CHECK: pxor
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; CHECK-DAG: psubq {{%xmm[0-9]+}}, [[SRC1:%xmm[0-9]+]]
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; CHECK-DAG: pandn {{%xmm[0-9]+}}, [[SRC2:%xmm[0-9]+]]
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; CHECK-DAG: pandn [[SRC1]], [[DST:%xmm[0-9]+]]
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; CHECK: por [[SRC2]], [[DST]]
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; CHECK: retq
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%1 = call <2 x i64> @llvm.sabsdiff.v2i64(<2 x i64> %a1, <2 x i64> %a2)
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ret <2 x i64> %1
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}
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@ -0,0 +1,29 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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declare <16 x i16> @llvm.sabsdiff.v16i16(<16 x i16>, <16 x i16>)
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define <16 x i16> @test_sabsdiff_v16i16_expand(<16 x i16> %a1, <16 x i16> %a2) {
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; CHECK-LABEL: test_sabsdiff_v16i16_expand:
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; CHECK: # BB#0:
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; CHECK: psubw
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; CHECK: pxor
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; CHECK: pcmpgtw
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; CHECK: movdqa
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; CHECK: pandn
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; CHECK: pxor
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; CHECK: psubw
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; CHECK: pcmpeqd
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; CHECK: pxor
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; CHECK: pandn
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; CHECK: por
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; CHECK: pcmpgtw
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; CHECK-DAG: psubw {{%xmm[0-9]+}}, [[SRC:%xmm[0-9]+]]
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; CHECK-DAG: pxor {{%xmm[0-9]+}}, [[DST:%xmm[0-9]+]]
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; CHECK: pandn [[SRC]], [[DST]]
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; CHECK: por
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; CHECK: movdqa
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; CHECK: retq
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%1 = call <16 x i16> @llvm.sabsdiff.v16i16(<16 x i16> %a1, <16 x i16> %a2)
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ret <16 x i16> %1
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}
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