big endian 32-bit systems (e.g. ppc32) want to return the high reg first, not
the lo-reg first. This is fallout from my ppc calling conv change yesterday, it fixes test/ExecutionEngine/2003-05-06-LivenessClobber.llx llvm-svn: 34983
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@ -1675,6 +1675,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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if (Tmp2.getValueType() != MVT::Vector) {
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SDOperand Lo, Hi;
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ExpandOp(Tmp2, Lo, Hi);
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// Big endian systems want the hi reg first.
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if (!TLI.isLittleEndian())
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std::swap(Lo, Hi);
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if (Hi.Val)
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Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
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else
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