From 13673ac704e5b95e24f2aab350a312597a38d406 Mon Sep 17 00:00:00 2001 From: Kai Nacke Date: Wed, 2 Apr 2014 18:40:43 +0000 Subject: [PATCH] [mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449 --- llvm/lib/Target/Mips/Mips64InstrInfo.td | 37 +++++++++++++++++------- llvm/lib/Target/Mips/MipsInstrFormats.td | 16 ++++++++++ llvm/test/CodeGen/Mips/octeon.ll | 14 +++++++++ llvm/test/MC/Mips/octeon-instructions.s | 32 ++++++++++++++++++-- 4 files changed, 87 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index d766a4eacd3c..7115d110c6c6 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -234,29 +234,45 @@ let Predicates = [HasCnMips] in { class Count1s: InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), - [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr>; + [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> { + let TwoOperandAliasConstraint = "$rd = $rs"; +} + +class ExtsCins: + InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1), + !strconcat(opstr, " $rt, $rs, $pos, $lenm1"), + [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))], + NoItinerary, FrmR, opstr> { + let TwoOperandAliasConstraint = "$rt = $rs"; +} class SetCC64_R : InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt), !strconcat(opstr, "\t$rd, $rs, $rt"), [(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))], - II_SEQ_SNE, FrmR, opstr>; + II_SEQ_SNE, FrmR, opstr> { + let TwoOperandAliasConstraint = "$rd = $rs"; +} // Unsigned Byte Add -def BADDu : InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt), - "baddu\t$rd, $rs, $rt", - [(set GPR64Opnd:$rd, (and (add GPR64Opnd:$rs, - GPR64Opnd:$rt), 255))], - II_BADDU, FrmR, "baddu">, ADD_FM<0x1c, 0x28> { - let isCommutable = 1; - let isReMaterializable = 1; -} +let Pattern = [(set GPR64Opnd:$rd, + (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in +def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>, + ADD_FM<0x1c, 0x28>; // Multiply Doubleword to GPR let Defs = [HI0, LO0, P0, P1, P2] in def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>, ADD_FM<0x1c, 0x03>; +// Extract a signed bit field /+32 +def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>; +def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>; + +// Clear and insert a bit field /+32 +def CINS : ExtsCins<"cins">, EXTS_FM<0x32>; +def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>; + // Move to multiplier/product register def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>; def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>; @@ -275,6 +291,7 @@ def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>; } } + //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Mips/MipsInstrFormats.td b/llvm/lib/Target/Mips/MipsInstrFormats.td index 5b690ac3b7e3..38fac886048a 100644 --- a/llvm/lib/Target/Mips/MipsInstrFormats.td +++ b/llvm/lib/Target/Mips/MipsInstrFormats.td @@ -489,6 +489,22 @@ class WAIT_FM : StdArch { let Inst{5-0} = 0x20; } +class EXTS_FM funct> : StdArch { + bits<5> rt; + bits<5> rs; + bits<5> pos; + bits<5> lenm1; + + bits<32> Inst; + + let Inst{31-26} = 0x1c; + let Inst{25-21} = rs; + let Inst{20-16} = rt; + let Inst{15-11} = lenm1; + let Inst{10-6} = pos; + let Inst{5-0} = funct; +} + class MTMR_FM funct> : StdArch { bits<5> rs; diff --git a/llvm/test/CodeGen/Mips/octeon.ll b/llvm/test/CodeGen/Mips/octeon.ll index 092938a6b5c9..d5ff9bdf3608 100644 --- a/llvm/test/CodeGen/Mips/octeon.ll +++ b/llvm/test/CodeGen/Mips/octeon.ll @@ -1,6 +1,20 @@ ; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefix=OCTEON ; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=MIPS64 +define i64 @addi64(i64 %a, i64 %b) nounwind { +entry: +; OCTEON-LABEL: addi64: +; OCTEON: jr $ra +; OCTEON: baddu $2, $4, $5 +; MIPS64-LABEL: addi64: +; MIPS64: daddu +; MIPS64: jr +; MIPS64: andi + %add = add i64 %a, %b + %and = and i64 %add, 255 + ret i64 %and +} + define i64 @mul(i64 %a, i64 %b) nounwind { entry: ; OCTEON-LABEL: mul: diff --git a/llvm/test/MC/Mips/octeon-instructions.s b/llvm/test/MC/Mips/octeon-instructions.s index b1c065fa5ef6..0244e196204d 100644 --- a/llvm/test/MC/Mips/octeon-instructions.s +++ b/llvm/test/MC/Mips/octeon-instructions.s @@ -2,11 +2,22 @@ # CHECK: baddu $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x28] # CHECK: baddu $17, $18, $19 # encoding: [0x72,0x53,0x88,0x28] -# CHECK: dmul $9, $9, $6 # encoding: [0x71,0x26,0x48,0x03] +# CHECK: baddu $2, $2, $3 # encoding: [0x70,0x43,0x10,0x28] +# CHECK: cins $25, $10, 22, 2 # encoding: [0x71,0x59,0x15,0xb2] +# CHECK: cins $9, $9, 17, 29 # encoding: [0x71,0x29,0xec,0x72] +# CHECK: cins32 $15, $2, 18, 8 # encoding: [0x70,0x4f,0x44,0xb3] +# CHECK: cins32 $22, $22, 9, 22 # encoding: [0x72,0xd6,0xb2,0x73] # CHECK: dmul $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x03] # CHECK: dmul $19, $24, $25 # encoding: [0x73,0x19,0x98,0x03] +# CHECK: dmul $9, $9, $6 # encoding: [0x71,0x26,0x48,0x03] +# CHECK: dmul $21, $21, $25 # encoding: [0x72,0xb9,0xa8,0x03] # CHECK: dpop $9, $6 # encoding: [0x70,0xc0,0x48,0x2d] # CHECK: dpop $15, $22 # encoding: [0x72,0xc0,0x78,0x2d] +# CHECK: dpop $12, $12 # encoding: [0x71,0x80,0x60,0x2d] +# CHECK: exts $4, $25, 27, 15 # encoding: [0x73,0x24,0x7e,0xfa] +# CHECK: exts $15, $15, 17, 6 # encoding: [0x71,0xef,0x34,0x7a] +# CHECK: exts32 $4, $13, 10, 8 # encoding: [0x71,0xa4,0x42,0xbb] +# CHECK: exts32 $15, $15, 11, 20 # encoding: [0x71,0xef,0xa2,0xfb] # CHECK: mtm0 $15 # encoding: [0x71,0xe0,0x00,0x08] # CHECK: mtm1 $16 # encoding: [0x72,0x00,0x00,0x0c] # CHECK: mtm2 $17 # encoding: [0x72,0x20,0x00,0x0d] @@ -15,16 +26,30 @@ # CHECK: mtp2 $20 # encoding: [0x72,0x80,0x00,0x0b] # CHECK: pop $9, $6 # encoding: [0x70,0xc0,0x48,0x2c] # CHECK: pop $8, $19 # encoding: [0x72,0x60,0x40,0x2c] +# CHECK: pop $2, $2 # encoding: [0x70,0x40,0x10,0x2c] # CHECK: seq $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2a] +# CHECK: seq $6, $6, $24 # encoding: [0x70,0xd8,0x30,0x2a] # CHECK: sne $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2b] +# CHECK: sne $23, $23, $20 # encoding: [0x72,0xf4,0xb8,0x2b] baddu $9, $6, $7 baddu $17, $18, $19 - dmul $9, $6 + baddu $2, $3 + cins $25, $10, 22, 2 + cins $9, 17, 29 + cins32 $15, $2, 18, 8 + cins32 $22, 9, 22 dmul $9, $6, $7 dmul $19, $24, $25 + dmul $9, $6 + dmul $21, $25 dpop $9, $6 dpop $15, $22 + dpop $12 + exts $4, $25, 27, 15 + exts $15, 17, 6 + exts32 $4, $13, 10, 8 + exts32 $15, 11, 20 mtm0 $15 mtm1 $16 mtm2 $17 @@ -33,5 +58,8 @@ mtp2 $20 pop $9, $6 pop $8, $19 + pop $2 seq $25, $23, $24 + seq $6, $24 sne $25, $23, $24 + sne $23, $20