Change fp to sint legalization on x86-32 to do 2 x i32
loads instead of 1 x i64 loads. This doesn't change any functionality yet. llvm-svn: 43068
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@ -3952,8 +3952,18 @@ SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Ops[] = { Chain, Value, StackSlot };
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SDOperand Ops[] = { Chain, Value, StackSlot };
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SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
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SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
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// Load the result.
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// Load the result. If this is an i64 load on an x86-32 host, expand the
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return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
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// load.
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if (Op.getValueType() != MVT::i64 || Subtarget->is64Bit())
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return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
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SDOperand Lo = DAG.getLoad(MVT::i32, FIST, StackSlot, NULL, 0);
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StackSlot = DAG.getNode(ISD::ADD, StackSlot.getValueType(), StackSlot,
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DAG.getConstant(StackSlot.getValueType(), 4));
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SDOperand Hi = DAG.getLoad(MVT::i32, FIST, StackSlot, NULL, 0);
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return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
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}
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}
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SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
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SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
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