diff --git a/llvm/lib/Target/X86/X86InstrFPStack.td b/llvm/lib/Target/X86/X86InstrFPStack.td index d4798f2f659b..456cc7bd0636 100644 --- a/llvm/lib/Target/X86/X86InstrFPStack.td +++ b/llvm/lib/Target/X86/X86InstrFPStack.td @@ -119,17 +119,6 @@ let isTerminator = 1 in // a pattern) and the FPI instruction should have emission info (e.g. opcode // encoding and asm printing info). -// FPI - Floating Point Instruction template. -class FPI o, Format F, dag outs, dag ins, string asm> - : I {} - -// FpI_ - Floating Point Psuedo Instruction template. Not Predicated. -class FpI_ pattern> - : X86Inst<0, Pseudo, NoImm, outs, ins, ""> { - let FPForm = fp; let FPFormBits = FPForm.Value; - let Pattern = pattern; -} - // Random Pseudo Instructions. def FpGETRESULT32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, [(set RFP32:$dst, X86fpget)]>; // FPR = ST(0) diff --git a/llvm/lib/Target/X86/X86InstrFormats.td b/llvm/lib/Target/X86/X86InstrFormats.td new file mode 100644 index 000000000000..912376d19642 --- /dev/null +++ b/llvm/lib/Target/X86/X86InstrFormats.td @@ -0,0 +1,232 @@ +//===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// X86 Instruction Format Definitions. +// + +// Format specifies the encoding used by the instruction. This is part of the +// ad-hoc solution used to emit machine instruction encodings by our machine +// code emitter. +class Format val> { + bits<6> Value = val; +} + +def Pseudo : Format<0>; def RawFrm : Format<1>; +def AddRegFrm : Format<2>; def MRMDestReg : Format<3>; +def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>; +def MRMSrcMem : Format<6>; +def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>; +def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>; +def MRM6r : Format<22>; def MRM7r : Format<23>; +def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; +def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; +def MRM6m : Format<30>; def MRM7m : Format<31>; +def MRMInitReg : Format<32>; + + +// ImmType - This specifies the immediate type used by an instruction. This is +// part of the ad-hoc solution used to emit machine instruction encodings by our +// machine code emitter. +class ImmType val> { + bits<3> Value = val; +} +def NoImm : ImmType<0>; +def Imm8 : ImmType<1>; +def Imm16 : ImmType<2>; +def Imm32 : ImmType<3>; +def Imm64 : ImmType<4>; + +// FPFormat - This specifies what form this FP instruction has. This is used by +// the Floating-Point stackifier pass. +class FPFormat val> { + bits<3> Value = val; +} +def NotFP : FPFormat<0>; +def ZeroArgFP : FPFormat<1>; +def OneArgFP : FPFormat<2>; +def OneArgFPRW : FPFormat<3>; +def TwoArgFP : FPFormat<4>; +def CompareFP : FPFormat<5>; +def CondMovFP : FPFormat<6>; +def SpecialFP : FPFormat<7>; + +// Prefix byte classes which are used to indicate to the ad-hoc machine code +// emitter that various prefix bytes are required. +class OpSize { bit hasOpSizePrefix = 1; } +class AdSize { bit hasAdSizePrefix = 1; } +class REX_W { bit hasREX_WPrefix = 1; } +class TB { bits<4> Prefix = 1; } +class REP { bits<4> Prefix = 2; } +class D8 { bits<4> Prefix = 3; } +class D9 { bits<4> Prefix = 4; } +class DA { bits<4> Prefix = 5; } +class DB { bits<4> Prefix = 6; } +class DC { bits<4> Prefix = 7; } +class DD { bits<4> Prefix = 8; } +class DE { bits<4> Prefix = 9; } +class DF { bits<4> Prefix = 10; } +class XD { bits<4> Prefix = 11; } +class XS { bits<4> Prefix = 12; } +class T8 { bits<4> Prefix = 13; } +class TA { bits<4> Prefix = 14; } + +class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, + string AsmStr> + : Instruction { + let Namespace = "X86"; + + bits<8> Opcode = opcod; + Format Form = f; + bits<6> FormBits = Form.Value; + ImmType ImmT = i; + bits<3> ImmTypeBits = ImmT.Value; + + dag OutOperandList = outs; + dag InOperandList = ins; + string AsmString = AsmStr; + + // + // Attributes specific to X86 instructions... + // + bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? + bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix? + + bits<4> Prefix = 0; // Which prefix byte does this inst have? + bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix? + FPFormat FPForm; // What flavor of FP instruction is this? + bits<3> FPFormBits = 0; +} + +class I o, Format f, dag outs, dag ins, string asm, list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} +class Ii8 o, Format f, dag outs, dag ins, string asm, list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} +class Ii16 o, Format f, dag outs, dag ins, string asm, list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} +class Ii32 o, Format f, dag outs, dag ins, string asm, list pattern> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} + +// FPStack Instruction Templates: +// FPI - Floating Point Instruction template. +class FPI o, Format F, dag outs, dag ins, string asm> + : I {} + +// FpI_ - Floating Point Psuedo Instruction template. Not Predicated. +class FpI_ pattern> + : X86Inst<0, Pseudo, NoImm, outs, ins, ""> { + let FPForm = fp; let FPFormBits = FPForm.Value; + let Pattern = pattern; +} + +// SSE1 Instruction Templates: +// +// SSI - SSE1 instructions with XS prefix. +// PSI - SSE1 instructions with TB prefix. +// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix. + +class SSI o, Format F, dag outs, dag ins, string asm, list pattern> + : I, XS, Requires<[HasSSE1]>; +class PSI o, Format F, dag outs, dag ins, string asm, list pattern> + : I, TB, Requires<[HasSSE1]>; +class PSIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TB, Requires<[HasSSE1]>; + +// SSE2 Instruction Templates: +// +// SDI - SSE2 instructions with XD prefix. +// PDI - SSE2 instructions with TB and OpSize prefixes. +// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes. + +class SDI o, Format F, dag outs, dag ins, string asm, list pattern> + : I, XD, Requires<[HasSSE2]>; +class PDI o, Format F, dag outs, dag ins, string asm, list pattern> + : I, TB, OpSize, Requires<[HasSSE2]>; +class PDIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, TB, OpSize, Requires<[HasSSE2]>; + +// SSE3 Instruction Templates: +// +// S3I - SSE3 instructions with TB and OpSize prefixes. +// S3SI - SSE3 instructions with XS prefix. +// S3DI - SSE3 instructions with XD prefix. + +class S3SI o, Format F, dag outs, dag ins, string asm, list pattern> + : I, XS, Requires<[HasSSE3]>; +class S3DI o, Format F, dag outs, dag ins, string asm, list pattern> + : I, XD, Requires<[HasSSE3]>; +class S3I o, Format F, dag outs, dag ins, string asm, list pattern> + : I, TB, OpSize, Requires<[HasSSE3]>; + + +// X86-64 Instruction templates... +// + +class RI o, Format F, dag outs, dag ins, string asm, list pattern> + : I, REX_W; +class RIi8 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii8, REX_W; +class RIi32 o, Format F, dag outs, dag ins, string asm, + list pattern> + : Ii32, REX_W; + +class RIi64 o, Format f, dag outs, dag ins, string asm, + list pattern> + : X86Inst, REX_W { + let Pattern = pattern; + let CodeSize = 3; +} + +class RSSI o, Format F, dag outs, dag ins, string asm, + list pattern> + : SSI, REX_W; +class RSDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : SDI, REX_W; +class RPDI o, Format F, dag outs, dag ins, string asm, + list pattern> + : PDI, REX_W; + +// MMX Instruction templates +// + +// MMXI - MMX instructions with TB prefix. +// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes. +// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. +// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. +// MMXID - MMX instructions with XD prefix. +// MMXIS - MMX instructions with XS prefix. +class MMXI o, Format F, dag outs, dag ins, string asm, list pattern> + : I, TB, Requires<[HasMMX]>; +class MMXRI o, Format F, dag outs, dag ins, string asm, list pattern> + : I, TB, REX_W, Requires<[HasMMX]>; +class MMX2I o, Format F, dag outs, dag ins, string asm, list pattern> + : I, TB, OpSize, Requires<[HasMMX]>; +class MMXIi8 o, Format F, dag outs, dag ins, string asm, list pattern> + : Ii8, TB, Requires<[HasMMX]>; +class MMXID o, Format F, dag outs, dag ins, string asm, list pattern> + : Ii8, XD, Requires<[HasMMX]>; +class MMXIS o, Format F, dag outs, dag ins, string asm, list pattern> + : Ii8, XS, Requires<[HasMMX]>; + diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 0f5a1dc29cc8..de292c9cad33 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -152,29 +152,6 @@ def addr : ComplexPattern; def lea32addr : ComplexPattern; -//===----------------------------------------------------------------------===// -// X86 Instruction Format Definitions. -// - -// Format specifies the encoding used by the instruction. This is part of the -// ad-hoc solution used to emit machine instruction encodings by our machine -// code emitter. -class Format val> { - bits<6> Value = val; -} - -def Pseudo : Format<0>; def RawFrm : Format<1>; -def AddRegFrm : Format<2>; def MRMDestReg : Format<3>; -def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>; -def MRMSrcMem : Format<6>; -def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>; -def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>; -def MRM6r : Format<22>; def MRM7r : Format<23>; -def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; -def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; -def MRM6m : Format<30>; def MRM7m : Format<31>; -def MRMInitReg : Format<32>; - //===----------------------------------------------------------------------===// // X86 Instruction Predicate Definitions. def HasMMX : Predicate<"Subtarget->hasMMX()">; @@ -190,84 +167,10 @@ def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">; def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; //===----------------------------------------------------------------------===// -// X86 specific pattern fragments. +// X86 Instruction Format Definitions. // -// ImmType - This specifies the immediate type used by an instruction. This is -// part of the ad-hoc solution used to emit machine instruction encodings by our -// machine code emitter. -class ImmType val> { - bits<3> Value = val; -} -def NoImm : ImmType<0>; -def Imm8 : ImmType<1>; -def Imm16 : ImmType<2>; -def Imm32 : ImmType<3>; -def Imm64 : ImmType<4>; - -// FPFormat - This specifies what form this FP instruction has. This is used by -// the Floating-Point stackifier pass. -class FPFormat val> { - bits<3> Value = val; -} -def NotFP : FPFormat<0>; -def ZeroArgFP : FPFormat<1>; -def OneArgFP : FPFormat<2>; -def OneArgFPRW : FPFormat<3>; -def TwoArgFP : FPFormat<4>; -def CompareFP : FPFormat<5>; -def CondMovFP : FPFormat<6>; -def SpecialFP : FPFormat<7>; - - -class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, - string AsmStr> - : Instruction { - let Namespace = "X86"; - - bits<8> Opcode = opcod; - Format Form = f; - bits<6> FormBits = Form.Value; - ImmType ImmT = i; - bits<3> ImmTypeBits = ImmT.Value; - - dag OutOperandList = outs; - dag InOperandList = ins; - string AsmString = AsmStr; - - // - // Attributes specific to X86 instructions... - // - bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? - bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix? - - bits<4> Prefix = 0; // Which prefix byte does this inst have? - bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix? - FPFormat FPForm; // What flavor of FP instruction is this? - bits<3> FPFormBits = 0; -} - - -// Prefix byte classes which are used to indicate to the ad-hoc machine code -// emitter that various prefix bytes are required. -class OpSize { bit hasOpSizePrefix = 1; } -class AdSize { bit hasAdSizePrefix = 1; } -class REX_W { bit hasREX_WPrefix = 1; } -class TB { bits<4> Prefix = 1; } -class REP { bits<4> Prefix = 2; } -class D8 { bits<4> Prefix = 3; } -class D9 { bits<4> Prefix = 4; } -class DA { bits<4> Prefix = 5; } -class DB { bits<4> Prefix = 6; } -class DC { bits<4> Prefix = 7; } -class DD { bits<4> Prefix = 8; } -class DE { bits<4> Prefix = 9; } -class DF { bits<4> Prefix = 10; } -class XD { bits<4> Prefix = 11; } -class XS { bits<4> Prefix = 12; } -class T8 { bits<4> Prefix = 13; } -class TA { bits<4> Prefix = 14; } - +include "X86InstrFormats.td" //===----------------------------------------------------------------------===// // Pattern fragments... @@ -333,31 +236,6 @@ def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; -//===----------------------------------------------------------------------===// -// Instruction templates... -// - -class I o, Format f, dag outs, dag ins, string asm, list pattern> - : X86Inst { - let Pattern = pattern; - let CodeSize = 3; -} -class Ii8 o, Format f, dag outs, dag ins, string asm, list pattern> - : X86Inst { - let Pattern = pattern; - let CodeSize = 3; -} -class Ii16 o, Format f, dag outs, dag ins, string asm, list pattern> - : X86Inst { - let Pattern = pattern; - let CodeSize = 3; -} -class Ii32 o, Format f, dag outs, dag ins, string asm, list pattern> - : X86Inst { - let Pattern = pattern; - let CodeSize = 3; -} - //===----------------------------------------------------------------------===// // Instruction list... // @@ -2653,6 +2531,12 @@ def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt), include "X86InstrFPStack.td" +//===----------------------------------------------------------------------===// +// X86-64 Support +//===----------------------------------------------------------------------===// + +include "X86InstrX86-64.td" + //===----------------------------------------------------------------------===// // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2) //===----------------------------------------------------------------------===// @@ -2664,9 +2548,3 @@ include "X86InstrMMX.td" //===----------------------------------------------------------------------===// include "X86InstrSSE.td" - -//===----------------------------------------------------------------------===// -// X86-64 Support -//===----------------------------------------------------------------------===// - -include "X86InstrX86-64.td" diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td index eed8843b389c..470d7c41c41c 100644 --- a/llvm/lib/Target/X86/X86InstrMMX.td +++ b/llvm/lib/Target/X86/X86InstrMMX.td @@ -13,29 +13,6 @@ // //===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// Instruction templates -//===----------------------------------------------------------------------===// - -// MMXI - MMX instructions with TB prefix. -// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes. -// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. -// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. -// MMXID - MMX instructions with XD prefix. -// MMXIS - MMX instructions with XS prefix. -class MMXI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, TB, Requires<[HasMMX]>; -class MMXRI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, TB, REX_W, Requires<[HasMMX]>; -class MMX2I o, Format F, dag outs, dag ins, string asm, list pattern> - : I, TB, OpSize, Requires<[HasMMX]>; -class MMXIi8 o, Format F, dag outs, dag ins, string asm, list pattern> - : Ii8, TB, Requires<[HasMMX]>; -class MMXID o, Format F, dag outs, dag ins, string asm, list pattern> - : Ii8, XD, Requires<[HasMMX]>; -class MMXIS o, Format F, dag outs, dag ins, string asm, list pattern> - : Ii8, XS, Requires<[HasMMX]>; - // Some 'special' instructions def IMPLICIT_DEF_VR64 : I<0, Pseudo, (outs VR64:$dst), (ins), "#IMPLICIT_DEF $dst", diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 327e44ccbd5c..d6ba5ded98e5 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -277,20 +277,6 @@ let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. // SSE1 Instructions //===----------------------------------------------------------------------===// -// SSE1 Instruction Templates: -// -// SSI - SSE1 instructions with XS prefix. -// PSI - SSE1 instructions with TB prefix. -// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix. - -class SSI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, XS, Requires<[HasSSE1]>; -class PSI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, TB, Requires<[HasSSE1]>; -class PSIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TB, Requires<[HasSSE1]>; - // Move Instructions def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src), "movss {$src, $dst|$dst, $src}", []>; @@ -947,20 +933,6 @@ def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src), // SSE2 Instructions //===----------------------------------------------------------------------===// -// SSE2 Instruction Templates: -// -// SDI - SSE2 instructions with XD prefix. -// PDI - SSE2 instructions with TB and OpSize prefixes. -// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes. - -class SDI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, XD, Requires<[HasSSE2]>; -class PDI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, TB, OpSize, Requires<[HasSSE2]>; -class PDIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TB, OpSize, Requires<[HasSSE2]>; - // Move Instructions def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src), "movsd {$src, $dst|$dst, $src}", []>; @@ -2180,19 +2152,6 @@ def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), // SSE3 Instructions //===----------------------------------------------------------------------===// -// SSE3 Instruction Templates: -// -// S3I - SSE3 instructions with TB and OpSize prefixes. -// S3SI - SSE3 instructions with XS prefix. -// S3DI - SSE3 instructions with XD prefix. - -class S3SI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, XS, Requires<[HasSSE3]>; -class S3DI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, XD, Requires<[HasSSE3]>; -class S3I o, Format F, dag outs, dag ins, string asm, list pattern> - : I, TB, OpSize, Requires<[HasSSE3]>; - // Move Instructions def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movshdup {$src, $dst|$dst, $src}", @@ -2655,3 +2614,11 @@ def : Pat<(store (v8i16 VR128:$src), addr:$dst), (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>; def : Pat<(store (v16i8 VR128:$src), addr:$dst), (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>; + +// (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) +def : Pat<(vector_extract + (bc_v4i32 (v4f32 (scalar_to_vector (loadf32 addr:$src)))), (iPTR 0)), + (MOV32rm addr:$src)>; +def : Pat<(vector_extract + (bc_v2i64 (v2f64 (scalar_to_vector (loadf64 addr:$src)))), (iPTR 0)), + (MOV64rm addr:$src)>; diff --git a/llvm/lib/Target/X86/X86InstrX86-64.td b/llvm/lib/Target/X86/X86InstrX86-64.td index ec0f47082946..caff76312e97 100644 --- a/llvm/lib/Target/X86/X86InstrX86-64.td +++ b/llvm/lib/Target/X86/X86InstrX86-64.td @@ -39,36 +39,6 @@ def lea64addr : ComplexPattern; -//===----------------------------------------------------------------------===// -// Instruction templates... -// - -class RI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, REX_W; -class RIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, REX_W; -class RIi32 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii32, REX_W; - -class RIi64 o, Format f, dag outs, dag ins, string asm, - list pattern> - : X86Inst, REX_W { - let Pattern = pattern; - let CodeSize = 3; -} - -class RSSI o, Format F, dag outs, dag ins, string asm, - list pattern> - : SSI, REX_W; -class RSDI o, Format F, dag outs, dag ins, string asm, - list pattern> - : SDI, REX_W; -class RPDI o, Format F, dag outs, dag ins, string asm, - list pattern> - : PDI, REX_W; - //===----------------------------------------------------------------------===// // Pattern fragments... // diff --git a/llvm/test/CodeGen/X86/2007-07-31-VInsertBug.ll b/llvm/test/CodeGen/X86/2007-07-31-VInsertBug.ll new file mode 100644 index 000000000000..50db1c62f292 --- /dev/null +++ b/llvm/test/CodeGen/X86/2007-07-31-VInsertBug.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin | %prcontext {pinsrw \$2} 1 | grep "movl \$1" +; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin | not grep movss + +@G = global <4 x float> zeroinitializer + +define void @test(i32 *%P1, i32* %P2, float *%FP) { + %T = load float* %FP + store i32 0, i32* %P1 + + %U = load <4 x float>* @G + store i32 1, i32* %P1 + %V = insertelement <4 x float> %U, float %T, i32 1 + store <4 x float> %V, <4 x float>* @G + + ret void +}