[ARM] Use ADDCARRY / SUBCARRY
This is a preparatory step for D34515 and also is being recommitted as its first version caused PR34045. This change: - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32 - lowering is done by first converting the boolean value into the carry flag using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two operations does the actual addition. - for subtraction, given that ISD::SUBCARRY second result is actually a borrow, we need to invert the value of the second operand and result before and after using ARMISD::SUBE. We need to invert the carry result of ARMISD::SUBE to preserve the semantics. - given that the generic combiner may lower ISD::ADDCARRY and ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering as well otherwise i64 operations now would require branches. This implies updating the corresponding test for unsigned. - add new combiner to remove the redundant conversions from/to carry flags to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C - fixes PR34045 Differential Revision: https://reviews.llvm.org/D35192 llvm-svn: 312898
This commit is contained in:
Roger Ferrer Ibanez
parent
7af729b3d2
commit
12b20f2307
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@ -802,6 +802,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::SSUBO, MVT::i32, Custom);
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setOperationAction(ISD::USUBO, MVT::i32, Custom);
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setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
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setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
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// i64 operation support.
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setOperationAction(ISD::MUL, MVT::i64, Expand);
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setOperationAction(ISD::MULHU, MVT::i32, Expand);
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@ -3953,7 +3956,7 @@ ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
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}
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SDValue
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ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
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ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
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// Let legalize expand this if it isn't a legal type yet.
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if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
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return SDValue();
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@ -3975,6 +3978,66 @@ ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
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return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
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}
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static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
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SelectionDAG &DAG) {
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SDLoc DL(BoolCarry);
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EVT CarryVT = BoolCarry.getValueType();
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APInt NegOne = APInt::getAllOnesValue(CarryVT.getScalarSizeInBits());
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// This converts the boolean value carry into the carry flag by doing
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// ARMISD::ADDC Carry, ~0
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return DAG.getNode(ARMISD::ADDC, DL, DAG.getVTList(CarryVT, MVT::i32),
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BoolCarry, DAG.getConstant(NegOne, DL, CarryVT));
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}
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static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
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SelectionDAG &DAG) {
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SDLoc DL(Flags);
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// Now convert the carry flag into a boolean carry. We do this
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// using ARMISD:ADDE 0, 0, Carry
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return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
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DAG.getConstant(0, DL, MVT::i32),
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DAG.getConstant(0, DL, MVT::i32), Flags);
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}
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SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
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SelectionDAG &DAG) const {
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// Let legalize expand this if it isn't a legal type yet.
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if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
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return SDValue();
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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SDLoc dl(Op);
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EVT VT = Op.getValueType();
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SDVTList VTs = DAG.getVTList(VT, MVT::i32);
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SDValue Value;
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SDValue Overflow;
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switch (Op.getOpcode()) {
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default:
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llvm_unreachable("Unknown overflow instruction!");
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case ISD::UADDO:
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Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
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// Convert the carry flag into a boolean value.
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Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
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break;
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case ISD::USUBO: {
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Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
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// Convert the carry flag into a boolean value.
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Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
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// ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
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// value. So compute 1 - C.
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Overflow = DAG.getNode(ISD::SUB, dl, VTs,
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DAG.getConstant(1, dl, MVT::i32), Overflow);
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break;
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}
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}
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return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
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}
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SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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SDValue Cond = Op.getOperand(0);
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SDValue SelectTrue = Op.getOperand(1);
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@ -7380,6 +7443,53 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
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Op.getOperand(1), Op.getOperand(2));
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}
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static SDValue LowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) {
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SDNode *N = Op.getNode();
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EVT VT = N->getValueType(0);
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SDVTList VTs = DAG.getVTList(VT, MVT::i32);
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SDValue Carry = Op.getOperand(2);
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EVT CarryVT = Carry.getValueType();
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SDLoc DL(Op);
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APInt NegOne = APInt::getAllOnesValue(CarryVT.getScalarSizeInBits());
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SDValue Result;
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if (Op.getOpcode() == ISD::ADDCARRY) {
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// This converts the boolean value carry into the carry flag.
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Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG);
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// Do the addition proper using the carry flag we wanted.
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Result = DAG.getNode(ARMISD::ADDE, DL, VTs, Op.getOperand(0),
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Op.getOperand(1), Carry.getValue(1));
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// Now convert the carry flag into a boolean value.
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Carry = ConvertCarryFlagToBooleanCarry(Result.getValue(1), VT, DAG);
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} else {
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// ARMISD::SUBE expects a carry not a borrow like ISD::SUBCARRY so we
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// have to invert the carry first.
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Carry =
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DAG.getNode(ISD::SUB, DL, VTs, DAG.getConstant(1, DL, MVT::i32), Carry);
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// This converts the boolean value carry into the carry flag.
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Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG);
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// Do the subtraction proper using the carry flag we wanted.
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Result = DAG.getNode(ARMISD::SUBE, DL, VTs, Op.getOperand(0),
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Op.getOperand(1), Carry.getValue(1));
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// Now convert the carry flag into a boolean value.
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Carry = ConvertCarryFlagToBooleanCarry(Result.getValue(1), VT, DAG);
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// But the carry returned by ARMISD::SUBE is not a borrow as expected
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// by ISD::SUBCARRY, so compute 1 - C.
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Carry =
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DAG.getNode(ISD::SUB, DL, VTs, DAG.getConstant(1, DL, MVT::i32), Carry);
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}
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// Return both values.
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return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Carry);
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}
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SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
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assert(Subtarget->isTargetDarwin());
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@ -7734,11 +7844,14 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::ADDE:
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case ISD::SUBC:
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case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
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case ISD::ADDCARRY:
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case ISD::SUBCARRY: return LowerADDSUBCARRY(Op, DAG);
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case ISD::SADDO:
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case ISD::UADDO:
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case ISD::SSUBO:
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return LowerSignedALUO(Op, DAG);
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case ISD::UADDO:
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case ISD::USUBO:
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return LowerXALUO(Op, DAG);
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return LowerUnsignedALUO(Op, DAG);
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case ISD::ATOMIC_LOAD:
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case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
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case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
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@ -9687,11 +9800,11 @@ static SDValue AddCombineTo64bitMLAL(SDNode *AddeNode,
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// a S/UMLAL instruction.
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// UMUL_LOHI
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// / :lo \ :hi
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// / \ [no multiline comment]
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// loAdd -> ADDE |
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// \ :glue /
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// \ /
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// ADDC <- hiAdd
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// V \ [no multiline comment]
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// loAdd -> ADDC |
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// \ :carry /
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// V V
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// ADDE <- hiAdd
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//
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assert(AddeNode->getOpcode() == ARMISD::ADDE && "Expect an ADDE");
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@ -9699,7 +9812,7 @@ static SDValue AddCombineTo64bitMLAL(SDNode *AddeNode,
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AddeNode->getOperand(2).getValueType() == MVT::i32 &&
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"ADDE node has the wrong inputs");
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// Check that we have a glued ADDC node.
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// Check that we are chained to the right ADDC node.
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SDNode* AddcNode = AddeNode->getOperand(2).getNode();
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if (AddcNode->getOpcode() != ARMISD::ADDC)
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return SDValue();
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@ -9750,7 +9863,7 @@ static SDValue AddCombineTo64bitMLAL(SDNode *AddeNode,
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SDValue* LoMul = nullptr;
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SDValue* LowAdd = nullptr;
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// Ensure that ADDE is from high result of ISD::SMUL_LOHI.
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// Ensure that ADDE is from high result of ISD::xMUL_LOHI.
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if ((AddeOp0 != MULOp.getValue(1)) && (AddeOp1 != MULOp.getValue(1)))
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return SDValue();
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@ -9775,6 +9888,11 @@ static SDValue AddCombineTo64bitMLAL(SDNode *AddeNode,
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if (!LoMul)
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return SDValue();
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// If HiAdd is a predecessor of ADDC, the replacement below will create a
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// cycle.
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if (AddcNode->isPredecessorOf(HiAdd->getNode()))
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return SDValue();
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// Create the merged node.
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SelectionDAG &DAG = DCI.DAG;
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@ -9877,8 +9995,22 @@ static SDValue PerformUMLALCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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static SDValue PerformAddcSubcCombine(SDNode *N, SelectionDAG &DAG,
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static SDValue PerformAddcSubcCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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const ARMSubtarget *Subtarget) {
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SelectionDAG &DAG(DCI.DAG);
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if (N->getOpcode() == ARMISD::ADDC) {
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// (ADDC (ADDE 0, 0, C), -1) -> C
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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if (LHS->getOpcode() == ARMISD::ADDE &&
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isNullConstant(LHS->getOperand(0)) &&
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isNullConstant(LHS->getOperand(1)) && isAllOnesConstant(RHS)) {
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return DCI.CombineTo(N, SDValue(N, 0), LHS->getOperand(2));
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}
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}
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if (Subtarget->isThumb1Only()) {
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SDValue RHS = N->getOperand(1);
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
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@ -11767,6 +11899,14 @@ static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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static const APInt *isPowerOf2Constant(SDValue V) {
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
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if (!C)
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return nullptr;
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const APInt *CV = &C->getAPIntValue();
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return CV->isPowerOf2() ? CV : nullptr;
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}
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SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &DAG) const {
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// If we have a CMOV, OR and AND combination such as:
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// if (x & CN)
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@ -11795,8 +11935,8 @@ SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &D
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SDValue And = CmpZ->getOperand(0);
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if (And->getOpcode() != ISD::AND)
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return SDValue();
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ConstantSDNode *AndC = dyn_cast<ConstantSDNode>(And->getOperand(1));
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if (!AndC || !AndC->getAPIntValue().isPowerOf2())
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const APInt *AndC = isPowerOf2Constant(And->getOperand(1));
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if (!AndC)
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return SDValue();
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SDValue X = And->getOperand(0);
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@ -11836,7 +11976,7 @@ SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &D
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SDValue V = Y;
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SDLoc dl(X);
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EVT VT = X.getValueType();
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unsigned BitInX = AndC->getAPIntValue().logBase2();
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unsigned BitInX = AndC->logBase2();
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if (BitInX != 0) {
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// We must shift X first.
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@ -11997,7 +12137,7 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
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case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
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case ARMISD::ADDC:
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case ARMISD::SUBC: return PerformAddcSubcCombine(N, DCI.DAG, Subtarget);
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case ARMISD::SUBC: return PerformAddcSubcCombine(N, DCI, Subtarget);
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case ARMISD::SUBE: return PerformAddeSubeCombine(N, DCI.DAG, Subtarget);
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case ARMISD::BFI: return PerformBFICombine(N, DCI);
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case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
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@ -12693,10 +12833,17 @@ void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
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case ARMISD::ADDE:
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case ARMISD::SUBC:
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case ARMISD::SUBE:
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// These nodes' second result is a boolean
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if (Op.getResNo() == 0)
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break;
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// Special cases when we convert a carry to a boolean.
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if (Op.getResNo() == 0) {
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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// (ADDE 0, 0, C) will give us a single bit.
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if (Op->getOpcode() == ARMISD::ADDE && isNullConstant(LHS) &&
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isNullConstant(RHS)) {
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Known.Zero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
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return;
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}
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}
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break;
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case ARMISD::CMOV: {
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// Bits are known zero/one if known on the LHS and RHS.
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@ -625,7 +625,8 @@ class InstrItineraryData;
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SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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@ -1,4 +1,6 @@
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; RUN: llc < %s -mtriple=arm-linux -mcpu=generic | FileCheck %s
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; RUN: llc < %s -mtriple=arm-linux -mcpu=generic -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
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; RUN: llc < %s -mtriple=thumbv6m-eabi -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=THUMBV6
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; RUN: llc < %s -mtriple=thumbv7-eabi -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=THUMBV7
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define i32 @uadd_overflow(i32 %a, i32 %b) #0 {
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%sadd = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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@ -7,10 +9,19 @@ define i32 @uadd_overflow(i32 %a, i32 %b) #0 {
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ret i32 %2
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; CHECK-LABEL: uadd_overflow:
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; CHECK: add r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]]
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; CHECK: mov r[[R1]], #1
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; CHECK: cmp r[[R2]], r[[R0]]
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; CHECK: movhs r[[R1]], #0
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; ARM: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
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; ARM: mov r[[R2:[0-9]+]], #0
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; ARM: adc r[[R0]], r[[R2]], #0
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; THUMBV6: movs r[[R2:[0-9]+]], #0
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; THUMBV6: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
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; THUMBV6: adcs r[[R2]], r[[R2]]
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; THUMBV6: mov r[[R0]], r[[R2]]
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; THUMBV7: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
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; THUMBV7: mov.w r[[R2:[0-9]+]], #0
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; THUMBV7: adc r[[R0]], r[[R2]], #0
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}
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@ -21,10 +32,26 @@ define i32 @sadd_overflow(i32 %a, i32 %b) #0 {
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ret i32 %2
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; CHECK-LABEL: sadd_overflow:
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; CHECK: add r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]]
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; CHECK: mov r[[R1]], #1
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; CHECK: cmp r[[R2]], r[[R0]]
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; CHECK: movvc r[[R1]], #0
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; ARM: add r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]]
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; ARM: mov r[[R1]], #1
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; ARM: cmp r[[R2]], r[[R0]]
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; ARM: movvc r[[R1]], #0
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; THUMBV6: mov r[[R2:[0-9]+]], r[[R0:[0-9]+]]
|
||||
; THUMBV6: adds r[[R3:[0-9]+]], r[[R2]], r[[R1:[0-9]+]]
|
||||
; THUMBV6: movs r[[R0]], #0
|
||||
; THUMBV6: movs r[[R1]], #1
|
||||
; THUMBV6: cmp r[[R3]], r[[R2]]
|
||||
; THUMBV6: bvc .L[[LABEL:.*]]
|
||||
; THUMBV6: mov r[[R0]], r[[R1]]
|
||||
; THUMBV6: .L[[LABEL]]:
|
||||
|
||||
; THUMBV7: movs r[[R1]], #1
|
||||
; THUMBV7: cmp r[[R2]], r[[R0]]
|
||||
; THUMBV7: it vc
|
||||
; THUMBV7: movvc r[[R1]], #0
|
||||
; THUMBV7: mov r[[R0]], r[[R1]]
|
||||
}
|
||||
|
||||
define i32 @usub_overflow(i32 %a, i32 %b) #0 {
|
||||
|
|
@ -34,9 +61,26 @@ define i32 @usub_overflow(i32 %a, i32 %b) #0 {
|
|||
ret i32 %2
|
||||
|
||||
; CHECK-LABEL: usub_overflow:
|
||||
; CHECK: mov r[[R2]], #1
|
||||
; CHECK: cmp r[[R0]], r[[R1]]
|
||||
; CHECK: movhs r[[R2]], #0
|
||||
|
||||
; ARM: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
|
||||
; ARM: mov r[[R2:[0-9]+]], #0
|
||||
; ARM: adc r[[R0]], r[[R2]], #0
|
||||
; ARM: rsb r[[R0]], r[[R0]], #1
|
||||
|
||||
; THUMBV6: movs r[[R2:[0-9]+]], #0
|
||||
; THUMBV6: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
|
||||
; THUMBV6: adcs r[[R2]], r[[R2]]
|
||||
; THUMBV6: movs r[[R0]], #1
|
||||
; THUMBV6: subs r[[R0]], r[[R0]], r[[R2]]
|
||||
|
||||
; THUMBV7: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
|
||||
; THUMBV7: mov.w r[[R2:[0-9]+]], #0
|
||||
; THUMBV7: adc r[[R0]], r[[R2]], #0
|
||||
; THUMBV7: rsb.w r[[R0]], r[[R0]], #1
|
||||
|
||||
; We should know that the overflow is just 1 bit,
|
||||
; no need to clear any other bit
|
||||
; CHECK-NOT: and
|
||||
}
|
||||
|
||||
define i32 @ssub_overflow(i32 %a, i32 %b) #0 {
|
||||
|
|
@ -46,9 +90,23 @@ define i32 @ssub_overflow(i32 %a, i32 %b) #0 {
|
|||
ret i32 %2
|
||||
|
||||
; CHECK-LABEL: ssub_overflow:
|
||||
; CHECK: mov r[[R2]], #1
|
||||
; CHECK: cmp r[[R0]], r[[R1]]
|
||||
; CHECK: movvc r[[R2]], #0
|
||||
|
||||
; ARM: mov r[[R2]], #1
|
||||
; ARM: cmp r[[R0]], r[[R1]]
|
||||
; ARM: movvc r[[R2]], #0
|
||||
|
||||
; THUMBV6: movs r[[R0]], #0
|
||||
; THUMBV6: movs r[[R3:[0-9]+]], #1
|
||||
; THUMBV6: cmp r[[R2]], r[[R1:[0-9]+]]
|
||||
; THUMBV6: bvc .L[[LABEL:.*]]
|
||||
; THUMBV6: mov r[[R0]], r[[R3]]
|
||||
; THUMBV6: .L[[LABEL]]:
|
||||
|
||||
; THUMBV7: movs r[[R2:[0-9]+]], #1
|
||||
; THUMBV7: cmp r[[R0:[0-9]+]], r[[R1:[0-9]+]]
|
||||
; THUMBV7: it vc
|
||||
; THUMBV7: movvc r[[R2]], #0
|
||||
; THUMBV7: mov r[[R0]], r[[R2]]
|
||||
}
|
||||
|
||||
declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1
|
||||
|
|
|
|||
|
|
@ -0,0 +1,53 @@
|
|||
; RUN: llc < %s -mtriple thumbv7 | FileCheck %s
|
||||
|
||||
; ModuleID = 'bugpoint-reduced-simplified.bc'
|
||||
define hidden void @bn_mul_comba8(i32* nocapture %r, i32* nocapture readonly %a, i32* nocapture readonly %b) local_unnamed_addr {
|
||||
entry:
|
||||
; This test is actually checking that no cycle is introduced but at least we
|
||||
; want to see a couple of umull and one umlal in the output
|
||||
; CHECK: umull
|
||||
; CHECK: umull
|
||||
; CHECK: umlal
|
||||
%0 = load i32, i32* %a, align 4
|
||||
%conv = zext i32 %0 to i64
|
||||
%1 = load i32, i32* %b, align 4
|
||||
%conv2 = zext i32 %1 to i64
|
||||
%mul = mul nuw i64 %conv2, %conv
|
||||
%shr = lshr i64 %mul, 32
|
||||
%2 = load i32, i32* %a, align 4
|
||||
%conv13 = zext i32 %2 to i64
|
||||
%3 = load i32, i32* undef, align 4
|
||||
%conv15 = zext i32 %3 to i64
|
||||
%mul16 = mul nuw i64 %conv15, %conv13
|
||||
%add18 = add i64 %mul16, %shr
|
||||
%shr20 = lshr i64 %add18, 32
|
||||
%conv21 = trunc i64 %shr20 to i32
|
||||
%4 = load i32, i32* undef, align 4
|
||||
%conv34 = zext i32 %4 to i64
|
||||
%5 = load i32, i32* %b, align 4
|
||||
%conv36 = zext i32 %5 to i64
|
||||
%mul37 = mul nuw i64 %conv36, %conv34
|
||||
%conv38 = and i64 %add18, 4294967295
|
||||
%add39 = add i64 %mul37, %conv38
|
||||
%shr41 = lshr i64 %add39, 32
|
||||
%conv42 = trunc i64 %shr41 to i32
|
||||
%add43 = add i32 %conv42, %conv21
|
||||
%cmp44 = icmp ult i32 %add43, %conv42
|
||||
%c1.1 = zext i1 %cmp44 to i32
|
||||
%add65 = add i32 0, %c1.1
|
||||
%add86 = add i32 %add65, 0
|
||||
%add107 = add i32 %add86, 0
|
||||
%conv124 = zext i32 %add107 to i64
|
||||
%add125 = add i64 0, %conv124
|
||||
%conv145 = and i64 %add125, 4294967295
|
||||
%add146 = add i64 %conv145, 0
|
||||
%conv166 = and i64 %add146, 4294967295
|
||||
%add167 = add i64 %conv166, 0
|
||||
%conv187 = and i64 %add167, 4294967295
|
||||
%add188 = add i64 %conv187, 0
|
||||
%conv189 = trunc i64 %add188 to i32
|
||||
%arrayidx200 = getelementptr inbounds i32, i32* %r, i32 3
|
||||
store i32 %conv189, i32* %arrayidx200, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue