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[NVPTX] Add support for envreg reads 

llvm-svn: 211930
This commit is contained in:
Justin Holewinski 2014-06-27 18:35:21 +00:00
parent 602fa5b5d1
commit 124fc1951f
4 changed files with 314 additions and 1 deletions
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130
llvm/include/llvm/IR/IntrinsicsNVVM.td
View File

@ -889,6 +889,136 @@ def int_nvvm_compiler_error :
def int_nvvm_compiler_warn :
Intrinsic<[], [llvm_anyptr_ty], [], "llvm.nvvm.compiler.warn">;
// Environment register read
def int_nvvm_read_ptx_sreg_envreg0
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg0">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg0">;
def int_nvvm_read_ptx_sreg_envreg1
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg1">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg1">;
def int_nvvm_read_ptx_sreg_envreg2
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg2">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg2">;
def int_nvvm_read_ptx_sreg_envreg3
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg3">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg3">;
def int_nvvm_read_ptx_sreg_envreg4
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg4">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg4">;
def int_nvvm_read_ptx_sreg_envreg5
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg5">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg5">;
def int_nvvm_read_ptx_sreg_envreg6
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg6">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg6">;
def int_nvvm_read_ptx_sreg_envreg7
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg7">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg7">;
def int_nvvm_read_ptx_sreg_envreg8
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg8">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg8">;
def int_nvvm_read_ptx_sreg_envreg9
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg9">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg9">;
def int_nvvm_read_ptx_sreg_envreg10
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg10">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg10">;
def int_nvvm_read_ptx_sreg_envreg11
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg11">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg11">;
def int_nvvm_read_ptx_sreg_envreg12
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg12">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg12">;
def int_nvvm_read_ptx_sreg_envreg13
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg13">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg13">;
def int_nvvm_read_ptx_sreg_envreg14
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg14">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg14">;
def int_nvvm_read_ptx_sreg_envreg15
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg15">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg15">;
def int_nvvm_read_ptx_sreg_envreg16
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg16">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg16">;
def int_nvvm_read_ptx_sreg_envreg17
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg17">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg17">;
def int_nvvm_read_ptx_sreg_envreg18
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg18">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg18">;
def int_nvvm_read_ptx_sreg_envreg19
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg19">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg19">;
def int_nvvm_read_ptx_sreg_envreg20
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg20">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg20">;
def int_nvvm_read_ptx_sreg_envreg21
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg21">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg21">;
def int_nvvm_read_ptx_sreg_envreg22
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg22">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg22">;
def int_nvvm_read_ptx_sreg_envreg23
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg23">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg23">;
def int_nvvm_read_ptx_sreg_envreg24
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg24">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg24">;
def int_nvvm_read_ptx_sreg_envreg25
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg25">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg25">;
def int_nvvm_read_ptx_sreg_envreg26
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg26">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg26">;
def int_nvvm_read_ptx_sreg_envreg27
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg27">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg27">;
def int_nvvm_read_ptx_sreg_envreg28
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg28">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg28">;
def int_nvvm_read_ptx_sreg_envreg29
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg29">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg29">;
def int_nvvm_read_ptx_sreg_envreg30
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg30">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg30">;
def int_nvvm_read_ptx_sreg_envreg31
: Intrinsic<[llvm_i32_ty], [], [IntrNoMem],
"llvm.nvvm.read.ptx.sreg.envreg31">,
GCCBuiltin<"__nvvm_read_ptx_sreg_envreg31">;
// Texture Fetch
def int_nvvm_tex_1d_v4f32_i32

39
llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
View File

@ -1689,6 +1689,45 @@ def INT_NVVM_COMPILER_ERROR_64 : NVPTXInst<(outs), (ins Int64Regs:$a),
[(int_nvvm_compiler_error Int64Regs:$a)]>;
// Special register reads
def MOV_SPECIAL : NVPTXInst<(outs Int32Regs:$d),
(ins SpecialRegs:$r),
"mov.b32\t$d, $r;", []>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg0), (MOV_SPECIAL ENVREG0)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg1), (MOV_SPECIAL ENVREG1)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg2), (MOV_SPECIAL ENVREG2)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg3), (MOV_SPECIAL ENVREG3)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg4), (MOV_SPECIAL ENVREG4)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg5), (MOV_SPECIAL ENVREG5)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg6), (MOV_SPECIAL ENVREG6)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg7), (MOV_SPECIAL ENVREG7)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg8), (MOV_SPECIAL ENVREG8)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg9), (MOV_SPECIAL ENVREG9)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg10), (MOV_SPECIAL ENVREG10)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg11), (MOV_SPECIAL ENVREG11)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg12), (MOV_SPECIAL ENVREG12)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg13), (MOV_SPECIAL ENVREG13)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg14), (MOV_SPECIAL ENVREG14)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg15), (MOV_SPECIAL ENVREG15)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg16), (MOV_SPECIAL ENVREG16)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg17), (MOV_SPECIAL ENVREG17)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg18), (MOV_SPECIAL ENVREG18)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg19), (MOV_SPECIAL ENVREG19)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg20), (MOV_SPECIAL ENVREG20)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg21), (MOV_SPECIAL ENVREG21)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg22), (MOV_SPECIAL ENVREG22)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg23), (MOV_SPECIAL ENVREG23)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg24), (MOV_SPECIAL ENVREG24)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg25), (MOV_SPECIAL ENVREG25)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg26), (MOV_SPECIAL ENVREG26)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg27), (MOV_SPECIAL ENVREG27)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg28), (MOV_SPECIAL ENVREG28)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg29), (MOV_SPECIAL ENVREG29)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg30), (MOV_SPECIAL ENVREG30)>;
def : Pat<(int_nvvm_read_ptx_sreg_envreg31), (MOV_SPECIAL ENVREG31)>;
//-----------------------------------
// Texture Intrinsics
//-----------------------------------

7
llvm/lib/Target/NVPTX/NVPTXRegisterInfo.td
View File

@ -46,6 +46,10 @@ foreach i = 0-4 in {
def da#i : NVPTXReg<"%da"#i>;
}
foreach i = 0-31 in {
def ENVREG#i : NVPTXReg<"%envreg"#i>;
}
//===----------------------------------------------------------------------===//
// Register classes
//===----------------------------------------------------------------------===//
@ -61,4 +65,5 @@ def Float32ArgRegs : NVPTXRegClass<[f32], 32, (add (sequence "fa%u", 0, 4))>;
def Float64ArgRegs : NVPTXRegClass<[f64], 64, (add (sequence "da%u", 0, 4))>;
// Read NVPTXRegisterInfo.cpp to see how VRFrame and VRDepot are used.
def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame, VRDepot)>;
def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame, VRDepot,
(sequence "ENVREG%u", 0, 31))>;

139
llvm/test/CodeGen/NVPTX/envreg.ll Normal file
View File

@ -0,0 +1,139 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg10()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg11()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg12()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg13()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg14()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg15()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg16()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg17()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg18()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg19()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg20()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg21()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg22()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg23()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg24()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg25()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg26()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg27()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg28()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg29()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg30()
declare i32 @llvm.nvvm.read.ptx.sreg.envreg31()
; CHECK: foo
define i32 @foo() {
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg0
%val0 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg0()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg1
%val1 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg1()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg2
%val2 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg2()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg3
%val3 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg3()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg4
%val4 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg4()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg5
%val5 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg5()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg6
%val6 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg6()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg7
%val7 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg7()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg8
%val8 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg8()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg9
%val9 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg9()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg10
%val10 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg10()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg11
%val11 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg11()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg12
%val12 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg12()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg13
%val13 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg13()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg14
%val14 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg14()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg15
%val15 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg15()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg16
%val16 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg16()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg17
%val17 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg17()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg18
%val18 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg18()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg19
%val19 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg19()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg20
%val20 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg20()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg21
%val21 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg21()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg22
%val22 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg22()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg23
%val23 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg23()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg24
%val24 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg24()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg25
%val25 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg25()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg26
%val26 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg26()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg27
%val27 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg27()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg28
%val28 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg28()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg29
%val29 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg29()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg30
%val30 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg30()
; CHECK: mov.b32 %r{{[0-9]+}}, %envreg31
%val31 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg31()
%ret0 = add i32 %val0, %val1
%ret1 = add i32 %ret0, %val2
%ret2 = add i32 %ret1, %val3
%ret3 = add i32 %ret2, %val4
%ret4 = add i32 %ret3, %val5
%ret5 = add i32 %ret4, %val6
%ret6 = add i32 %ret5, %val7
%ret7 = add i32 %ret6, %val8
%ret8 = add i32 %ret7, %val9
%ret9 = add i32 %ret8, %val10
%ret10 = add i32 %ret9, %val11
%ret11 = add i32 %ret10, %val12
%ret12 = add i32 %ret11, %val13
%ret13 = add i32 %ret12, %val14
%ret14 = add i32 %ret13, %val15
%ret15 = add i32 %ret14, %val16
%ret16 = add i32 %ret15, %val17
%ret17 = add i32 %ret16, %val18
%ret18 = add i32 %ret17, %val19
%ret19 = add i32 %ret18, %val20
%ret20 = add i32 %ret19, %val21
%ret21 = add i32 %ret20, %val22
%ret22 = add i32 %ret21, %val23
%ret23 = add i32 %ret22, %val24
%ret24 = add i32 %ret23, %val25
%ret25 = add i32 %ret24, %val26
%ret26 = add i32 %ret25, %val27
%ret27 = add i32 %ret26, %val28
%ret28 = add i32 %ret27, %val29
%ret29 = add i32 %ret28, %val30
%ret30 = add i32 %ret29, %val31
ret i32 %ret30
}